MT18VDDF12872 Datasheet, PDF (12/31 Pages) Micron Technology – DDR SDRAM REGISTERED DIMM

512MB, 1GB (x72, ECC, SR) PC3200
184-PIN DDR SDRAM RDIMM
Commands
Table 8, Commands Truth Table, and Table 9, DM
Operation Truth Table, provide a general reference of
available commands. For a more detailed description
of commands and operations, refer to the 256Mb or
512Mb DDR SDRAM component data sheet.
Table 8: Commands Truth Table
CKE is HIGH for all commands shown except SELF REFRESH; all states and sequences not shown are illegal or reserved
NAME (FUNCTION)
CS# RAS# CAS# WE# ADDR
DESELECT (NOP)
H
X
NO OPERATION (NOP)
L
H
ACTIVE (Select bank and activate row)
L
L
READ (Select bank and column, and start READ burst)
L
H
WRITE (Select bank and column, and start WRITE burst)
L
H
BURST TERMINATE
L
H
PRECHARGE (Deactivate row in bank or banks)
L
L
AUTO REFRESH or SELF REFRESH (Enter self refresh mode) L
L
LOAD MODE REGISTER
L
L
X
X
X
H
H
X
H
H Bank/Row
L
H Bank/Col
L
L Bank/Col
H
L
X
H
L
Code
L
H
X
L
L Op-Code
NOTES
1
1
2
3
3
4
5
6, 7
8
NOTE:
1. DESELECT and NOP are functionally interchangeable.
2. BA0–BA1 provide device bank address and A0–A12 provide row address.
3. BA0–BA1 provide device bank address; A0–A9, A11 (512MB) or A0–A9, A11, A12 (1GB) provide column address; A10
HIGH enables the auto precharge feature (nonpersistent), and A10 LOW disables the auto precharge feature.
4. Applies only to read bursts with auto precharge disabled; this command is undefined (and should not be used) for READ
bursts with auto precharge enabled and for WRITE bursts.
5. A10 LOW: BA0–BA1 determine which device bank is precharged. A10 HIGH: all device banks are precharged and BA0–
BA1 are “Don’t Care.”
6. This command is AUTO REFRESH if CKE is HIGH, SELF REFRESH if CKE is LOW.
7. Internal refresh counter controls row addressing; all inputs and I/Os are “Don’t Care” except for CKE.
8. BA0–BA1 select either the mode register or the extended mode register (BA0 = 0, BA1 = 0 select the mode register; BA0
= 1, BA1 = 0 select extended mode register; other combinations of BA0-BA1 are reserved). A0–A12 provide the op-code
to be written to the selected mode register.
Table 9: DM Operation Truth Table
Used to mask write data; provided coincident with the corresponding data
NAME (FUNCTION)
WRITE Enable
WRITE Inhibit
DM
DQS
L
Valid
H
X
pdf: 09005aef80f6b913, source: 09005aef80f6b41c
DDAF18C64_128x72G.fm - Rev. C 9/04 EN
12
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