MT47H64M16HR-25EITH Datasheet, PDF (113/134 Pages) Micron Technology – DDR2 SDRAM MT47H256M4 – 32 Meg x 4 x 8 banks MT47H128M8 – 16 Meg x 8 x 8 banks MT47H64M16 – 8 Meg x 16 x 8 banks

1Gb: x4, x8, x16 DDR2 SDRAM
WRITE
Figure 65: WRITE – DM Operation
CK#
T0
CK
CKE
Command _NOP1
Address
A10
Bank select
DQS, DQS#
DQ7
DM
T1
T2
T3
T4
T5
T6 T6n T7 T7n T8
T9
T10
T11
tCK
tCH tCL
ACT
NOP1
WRITE2
NOP1
NOP1
NOP1
NOP1
NOP1
AL = 1
WL = 2
RA
Col n
RA
Bank x
3
Bank x
tRCD
tRAS
WL ±tDQSS (NOM)
6
tWPRE
D_nI
tDQSL tDQSH tWPST
NOP1
NOP1
PRE
tWR5
All banks
One bank
Bank x⁴
tRPA
Transitioning Data
Don’t Care
Notes:
1. NOP commands are shown for ease of illustration; other commands may be valid at
these times.
2. BL = 4, AL = 1, and WL = 2 in the case shown.
3. Disable auto precharge.
4. “Don’t Care” if A10 is HIGH at T11.
5. ^tWR starts at the end of the data burst regardless of the data mask condition.
6. Subsequent rising DQS signals must align to the clock within ^tDQSS.
7. DI n = data-in for column n; subsequent elements are applied in the programmed order.
8. ^tDSH is applicable during ^tDQSS (MIN) and is referenced from CK T6 or T7.
9. ^tDSS is applicable during ^tDQSS (MAX) and is referenced from CK T7 or T8.
PDF: 09005aef821ae8bf
1GbDDR2.pdf – Rev. V 6/10 EN
113
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