M25P40_12 Datasheet, PDF (10/59 Pages) Micron Technology – Micron M25P40 Serial Flash Embedded Memory

Micron M25P40 Serial Flash Embedded Memory
SPI Modes
Figure 4: Bus Master and Memory Devices on the SPI Bus
R
SPI interface with
(CPOL, CPHA) =
(0, 0) or (1, 1)
SDO
SDI
SCK
SPI Bus Master
R
CS3
CS2 CS1
VSS
VCC
C
VCC
DQ1 DQ0
VSS
C
DQ1 DQ0
VCC
VSS
C
VCC
DQ1 DQ0
VSS
SPI memory
R
device
SPI memory
R
device
SPI memory
device
S#
W# HOLD#
S#
W# HOLD#
S#
W# HOLD#
Notes:
1. WRITE PROTECT (W#) and HOLD# should be driven HIGH or LOW as appropriate.
2. Resistors (R) ensure that the memory device is not selected if the bus master leaves the
S# line HIGH-Z.
3. The bus master may enter a state where all I/O are HIGH-Z at the same time; for exam-
ple, when the bus master is reset. Therefore, the C must be connected to an external
pull-down resistor so that when all I/O are HIGH-Z, S# is pulled HIGH while C is pulled
LOW. This ensures that S# and C do not go HIGH at the same time and that the ^tSHCH
requirement is met.
4. The typical value of R is 100 kΩ, assuming that the time constant R × C_p (C_p = parasitic
capacitance of the bus line) is shorter than the time during which the bus master leaves
the SPI bus HIGH-Z.
5. Example: Given that C_p = 50 pF (R × C_p = 5μs), the application must ensure that the bus
master never leaves the SPI bus HIGH-Z for a time period shorter than 5μs.
PDF: 09005aef8456654f
m25p40.pdf - Rev. Y 8/12 EN
10
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