MT4LC8M8E1 Datasheet, PDF (1/20 Pages) Micron Technology – DRAM

DRAM
8 MEG x 8
FPM DRAM
MT4LC8M8E1, MT4LC8M8B6
For the latest data sheet, please refer to the Micron Web
site: www.micron.com/products/datasheets/dramds.html
FEATURES
• Single +3.3V ±0.3V power supply
• Industry-standard x8 pinout, timing, functions,
and packages
• 13 row, 10 column addresses (E1) or
12 row, 11 column addresses (B6)
• High-performance CMOS silicon-gate process
• All inputs, outputs and clocks are LVTTL-
compatible
• FAST PAGE MODE (FPM) access
• 4,096-cycle CAS#-BEFORE-RAS# (CBR) REFRESH
distributed across 64ms
• Optional self refresh (S) for low-power data
retention
OPTIONS
• Refresh Addressing
4,096 (4K) rows
8,192 (8K) rows
MARKING
B6
E1
• Plastic Packages
32-pin SOJ (400 mil)
DJ
32-pin TSOP (400 mil)
TG
• Timing
50ns access
-5
60ns access
-6
• Refresh Rates
Standard Refresh (64ms period)
Self Refresh (128ms period)
None
S*
NOTE: 1. The 8 Meg x 8 FPM DRAM base number
differentiates the offerings in one place—
MT4LC8M8E1. The fifth field distinguishes
various options: E1 designates an 8K refresh and
B6 designates a 4K refresh for FPM DRAMs.
2. The # symbol indicates signal is active LOW.
*Contact factory for availability
Part Number Example:
MT4LC8M8E1DJ-5
KEY TIMING PARAMETERS
SPEED
-5
-6
t_RC
90ns
110ns
t_RAC
50ns
60ns
t_PC
30ns
35ns
t_AA
25ns
30ns
t_CAC
13ns
15ns
PIN ASSIGNMENT (Top View)
32-Pin SOJ
32-Pin TSOP
VCC 1
DQ0 2
DQ1 3
DQ2 4
DQ3 5
NC 6
VCC 7
WE# 8
RAS# 9
A0 10
A1 11
A2 12
A3 13
A4 14
A5 15
VCC 16
32 VSS
31 DQ7
30 DQ6
29 DQ5
28 DQ4
27 Vss
VCC 1
DQ0 2
DQ1 3
DQ2 4
DQ3 5
NC 6
VCC 7
26 CAS#
WE# 8
25 OE#
RAS# 9
24 NC/A12** ^{A0 10}
23 A11
A1 11
22 A10
21 A9
20 A8
19 A7
A2 12
A3 13
A4 14
A5 15
VCC 16
18 A6
17 VSS
**A12 on E1 version, NC on B6 version
32 VSS
31 DQ7
30 DQ6
29 DQ5
28 DQ4
27 VSS
26 CAS#
25 OE#
24 NC/A12**
23 A11
22 A10
21 A9
20 A8
19 A7
18 A6
17 VSS
8 MEG x 8 FPM DRAM PART NUMBERS
PART NUMBER
MT4LC8M8E1DJ-x
MT4LC8M8E1DJ-x S
MT4LC8M8E1TG-x
MT4LC8M8E1TG-x S
MT4LC8M8B6DJ-x
MT4LC8M8B6DJ-x S
MT4LC8M8B6TG-x
MT4LC8M8B6TG-x S
REFRESH
ADDRESSING
8K
8K
8K
8K
4K
4K
4K
4K
PACKAGE REFRESH
SOJ
Standard
SOJ
Self
TSOP Standard
TSOP
Self
SOJ
Standard
SOJ
Self
TSOP
TSOP
Standard
Self
x = speed
GENERAL DESCRIPTION
The 8 Meg x 8 DRAMs are high-speed CMOS, dy-
namic random-access memory devices containing
67,108,864 bits organized in a x8 configuration. The
8 Meg x 8 DRAMs are functionally organized as 8,388,608
locations containing eight bits each. The 8,388,608
memory locations are arranged in 8,192 rows by 1,024
columns for the MT4LC8M8E1 or 4,096 rows by 2,048
columns for the MT4LC8M8B6. During READ or WRITE
cycles, each location is uniquely addressed via the
address bits. First, the row address is latched by the
8 Meg x 8 FPM DRAM
D19_2.p65 – Rev. 5/00
1
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2000, Micron Technology, Inc.