MT4LC16M4A7 Datasheet, PDF (1/20 Pages) Micron Technology – DRAM

DRAM
16 MEG x 4
FPM DRAM
MT4LC16M4A7, MT4LC16M4T8
For the latest data sheet, please refer to the Micron Web
site: www.micronsemi.com/mti/msp/html/datasheet.html
FEATURES
• Single +3.3V ±0.3V power supply
• Industry-standard x4 pinout, timing, functions,
and packages
• 13 row, 11 column addresses (A7)
12 row, 12 column addresses (T8)
• High-performance CMOS silicon-gate process
• All inputs, outputs and clocks are LVTTL-compat-
ible
• FAST-PAGE-MODE (FPM) access
• 4,096-cycle CAS#-BEFORE-RAS# (CBR) REFRESH
distributed across 64ms
• Optional self refresh (S) for low-power data
retention
OPTIONS
• Refresh Addressing
4,096 (4K) rows
8,192 (8K) rows
MARKING
T8
A7
• Plastic Packages
32-pin SOJ (400 mil)
DJ
32-pin TSOP (400 mil)
TG
• Timing
50ns access
-5
60ns access
-6
• Refresh Rates
Standard Refresh
Self Refresh (128ms period)
None
S*
NOTE: 1. The 16 Meg x 4 FPM DRAM base number
differentiates the offerings in one place—
MT4LC16M4A7. The fifth field distinguishes
various options: A7 designates an 8K refresh and
T8 designates a 4K refresh for FPM DRAMs.
2. The # symbol indicates signal is active LOW.
*Contact factory for availability
Part Number Example:
MT4LC16M4A7DJ
KEY TIMING PARAMETERS
SPEED
-5
-6
t_RC
90ns
110ns
t_RAC
50ns
60ns
t_PC
30ns
35ns
t_AA
25ns
30ns
t_CAC
13ns
15ns
PIN ASSIGNMENT (Top View)
32-Pin SOJ
32-Pin TSOP
VCC 1
DQ0 2
DQ1 3
NC 4
NC 5
NC 6
NC 7
WE# 8
RAS# 9
A0 10
A1 11
A2 12
A3 13
A4 14
A5 15
VCC 16
32 VSS
31 DQ3
30 DQ2
29 NC
28 NC
VCC 1
DQ0 2
DQ1 3
NC 4
NC 5
NC 6
27 NC
NC 7
26 CAS#
WE# 8
25 OE#
RAS# 9
24
A12/NC**
A0
A1
10
11
23 A11
A2 12
22 A10
A3 13
21 A9
A4 14
20 A8
19 A7
A5 15
VCC 16
18 A6
17 VSS
32 VSS
31 DQ3
30 DQ2
29 NC
28 NC
27 NC
26 CAS#
25 OE#
24 A12/NC**
23 A11
22 A10
21 A9
20 A8
19 A7
18 A6
17 VSS
**A12 on A7 version and NC on T8 version
16 MEG x 4 FPM DRAM PART NUMBERS
PART NUMBER
REFRESH
ADDRESSING PACKAGE REFRESH
MT4LC16M4A7DJ-x
8K
SOJ
Standard
MT4LC16M4A7DJ-x S
8K
SOJ
Self
MT4LC16M4A7TG-x
8K
MT4LC16M4A7TG-x S
8K
TSOP
TSOP
Standard
Self
MT4LC16M4T8DJ-x
4K
SOJ
Standard
MT4LC16M4T8DJ-x S
4K
SOJ
Self
MT4LC16M4T8TG-x
4K
TSOP Standard
MT4LC16M4T8TG-x S
4K
TSOP
Self
x = speed
GENERAL DESCRIPTION
The 16 Meg x 4 DRAMs are high-speed CMOS,
dynamic random-access memory devices contain-ing
67,108,864 bits organized in a x4 configuration. The
MT4LC16M4A7 and MT4LC16M4T8 are functionally
organized as 16,777,216 locations containing four bits
each. The 16,777,216 memory locations are arranged in
8,192 rows by 2,048 columns for the MT4LC16M4A7 or
4,096 rows by 4,096 columns for the MT4LC16M4T8.
During READ or WRITE cycles, each location is uniquely
16 Meg x 4 FPM DRAM
D21_2.p65 – Rev. 5/00
1
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2000, Micron Technology, Inc.