MT4C16270 Datasheet, PDF (1/22 Pages) Micron Technology – DRAM 256K X 16 DRAM 5V, EDO PAGE MODE

TECHNOLOGY, INC.
DRAM
MT4C16270
256K x 16 DRAM
256K x 16 DRAM
5V, EDO PAGE MODE
FEATURES
• Industry-standard x16 pinouts, timing, functions
and packages
• High-performance CMOS silicon-gate process
• Single +5V ±10% power supply*
• Low power, 3mW standby; 300mW active, typical
• All device pins are TTL-compatible
• 512-cycle refresh in 8ms (9 row- and 9 column
addresses)
• Refresh modes: RAS#-ONLY, CAS#-BEFORE-RAS#
(CBR) and HIDDEN
• Extended Data-Out (EDO) PAGE MODE access cycle
• BYTE WRITE and BYTE READ access cycles
OPTIONS
• Timing
40ns access
50ns access
60ns access
MARKING
-4*
-5*
-6
• Packages
Plastic SOJ (400 mil)
DJ
• Part Number Example: MT4C16270DJ-4
*40ns and 50ns access specifications are limited to a VCC range of ±5%.
Contact factory for availability.
KEY TIMING PARAMETERS
SPEED
-4
-5
-6
t_RC
75ns
100ns
110ns
t_RAC
40ns
50ns
60ns
t_PC
15ns
20ns
25ns
t_AA
20ns
25ns
30ns
t_CAC
12ns
15ns
15ns
t_CAS
6ns
8ns
10ns
t_CP
6ns
8ns
10ns
PIN ASSIGNMENT (Top View)
40-Pin SOJ
(DA-6)
Vcc 1
DQ1 2
DQ2 3
DQ3 4
DQ4 5
Vcc 6
DQ5 7
DQ6 8
DQ7 9
DQ8 10
NC 11
NC 12
WE# 13
RAS# 14
NC 15
A0 16
A1 17
A2 18
A3 19
Vcc 20
40 Vss
39 DQ16
38 DQ15
37 DQ14
36 DQ13
35 Vss
34 DQ12
33 DQ11
32 DQ10
31 DQ9
30 NC
29 CASL#
28 CASH#
27 OE#
26 A8
25 A7
24 A6
23 A5
22 A4
21 Vss
GENERAL DESCRIPTION
The MT4C16270 is a randomly accessed solid-state
memory containing 4,194,304 bits organized in a x16 con-
figuration. The MT4C16270 has both BYTE WRITE and
WORD WRITE access cycles via two CAS# pins.
The MT4C16270 CAS# function and timing are deter-
mined by the first CAS# (CASL# or CASH#) to transition
LOW and by the last to transition back HIGH. CASL# and
CASH# function in a similar manner to CAS# in that either
CASL# or CASH# will generate an internal CAS#. Use of
only one of the two results in a BYTE WRITE cycle. CASL#
transitioning LOW selects a WRITE cycle for the lower
byte (DQ1-DQ8) and CASH# transitioning LOW selects a
WRITE cycle for the upper byte (DQ9-DQ16). BYTE READ
cycles are achieved through CASL# or CASH# in the same
manner.
MT4C16270
W06.pm5 – Rev. 10/96
1
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©1996, Micron Technology, Inc.