MT48LC4M4A1 Datasheet, PDF (1/50 Pages) Micron Technology – SYNCHRONOUS DRAM

SYNCHRONOUS
DRAM
16 MEG: x4, x8
SDRAM
MT48LC4M4A1/A2 S - 2 Meg x 4 x 2 banks
MT48LC2M8A1/A2 S - 1 Meg x 8 x 2 banks
For the latest data sheet revisions, please refer to the
Micron Web site: www.micron.com/datasheets.
FEATURES
• PC100-compliant; includes CONCURRENT AUTO
PRECHARGE
• Fully synchronous; all signals registered on positive
edge of system clock
• Internal pipelined operation; column address can be
changed every clock cycle
• Internal banks for hiding row access/precharge
• Programmable burst lengths: 1, 2, 4, 8, or full page
• Auto Precharge and Auto Refresh Modes
• Self Refresh Mode
• 64ms, 4,096-cycle refresh
• LVTTL-compatible inputs and outputs
• Single +3.3V ±0.3V power supply
• Longer lead TSOP for improved reliability (OCPL*)
• One- and two-clock WRITE recovery (^tWR) versions
OPTIONS
• Configurations
4 Meg x 4 (2 Meg x 4 x 2 banks)
2 Meg x 8 (1 Meg x 8 x 2 banks)
MARKING
4M4
2M8
• WRITE Recovery (^tWR/^tDPL)
t_{WR = 1 CLK}
A1
t_{WR = 2 CLK (Contact factory for availability.)A2}
• Plastic Package - OCPL*
44-pin TSOP (400 mil)
TG
• Timing (Cycle Time)
8ns; ^tAC = 6ns @ CL = 3
-8B
10ns; ^tAC = 9ns @ CL = 2
-10
NOTE: The 16Mb SDRAM base number differentiates the
offerings in two places: MT48LC2M8A1 S. The fourth
field distinguishes the architecture offering: 4M4
designates 4 Meg x 4, and 2M8 designates 2 Meg x 8.
The fifth field distinguishes the WRITE recovery
offering: A1 designates one CLK and A2 designates two
CLKs.
Part Number Example:
MT48LC2M8A1TG-10 S
16Mb (x4/x8) SDRAM PART NUMBERS
PART NUMBER
MT48LC4M4A1TG S
MT48LC2M8A1TG S
ARCHITECTURE
4 Meg x 4 (^tWR = 1 CLK)
2 Meg x 8 (^tWR = 1 CLK)
PIN ASSIGNMENT (Top View)
x4
-
NC
-
DQ0
-
NC
-
DQ1
-
-
-
-
-
-
-
-
-
-
-
-
-
-
x8
VDD
DQ0
VssQ
DQ1
VDDQ
DQ2
VssQ
DQ3
VDDQ
NC
NC
WE#
CAS#
RAS#
CS#
BA
A10
A0
A1
A2
A3
VDD
44-Pin TSOP
1
44
2
43
3
42
4
41
5
40
6
39
7
38
8
37
9
36
10
35
11
34
12
33
13
32
14
31
15
30
16
29
17
28
18
27
19
26
20
25
21
24
22
23
x8 x4
Vss
DQ7
VssQ
DQ6
VDDQ
DQ5
VssQ
DQ4
VDDQ
NC
NC
DQM
CLK
CKE
NC
A9
A8
A7
A6
A5
A4
Vss
-
NC
-
DQ3
-
NC
-
DQ2
-
-
-
-
-
-
-
-
-
-
-
-
-
-
NOTE: The # symbol indicates signal is active LOW. A dash
(-) indicates x4 pin function is same as x8 pin
function.
Configuration
Refresh Count
Row Addressing
Bank Addressing
Column Addressing
4 MEG x 4
2 Meg x 4 x 2 banks
4K
2K (A0-A10)
2 (BA)
1K (A0-A9)
2 MEG x 8
1 Meg x 8 x 2 banks
4K
2K (A0-A10)
1 (BA)
512 (A0-A8)
KEY TIMING PARAMETERS
SPEED
GRADE
-8B
-10
-8B
-10
CLOCK
ACCESS TIME SETUP
FREQUENCY CL = 2** CL = 3** TIME
125 MHz
–
6ns
2ns
100 MHz
–
7.5ns 3ns
83 MHz
9ns
–
2ns
66 MHz
9ns
–
3ns
HOLD
TIME
1ns
1ns
1ns
1ns
* Off-center parting line
**CL = CAS (READ) latency
16 Meg: x4, x8 SDRAM
16MSDRAMx4x8_B.p65 – Rev. 5/98
1
©1998, Micron Technology, Inc.
PRODUCTS AND SPECIFICATIONS DISCUSSED HEREIN ARE SUBJECT TO CHANGE BY MICRON WITHOUT NOTICE.