MT46V16M8 Datasheet, PDF (1/9 Pages) Micron Technology – DOUBLE DATA RATE DDR SDRAM

DOUBLE DATA RATE
(DDR) SDRAM
PREVIEW^‡
128Mb: x8
DDR400 SDRAM Addendum
MT46V16M8 – 4 Meg x 8 x 4 banks
For the latest data sheet revisions, please refer to the Micron
Web site: www.micron.com/dramds
FEATURES
• 200 MHz Clock, 400 Mb/s/p data rate
• VDD = +2.65V ±0.10V
• VDDQ = +2.65V ±0.10V
• Bidirectional data strobe (DQS) transmitted/
received with data, i.e., source-synchronous data
capture
• Internal, pipelined double-data-rate (DDR)
architecture; two data accesses per clock cycle
• Differential clock inputs (CK and CK#)
• Commands entered on each positive CK edge
• DQS edge-aligned with data for READs; center-
aligned with data for WRITEs
• DLL to align DQ and DQS transitions with CK
• Four internal banks for concurrent operation
• Data mask (DM) for masking write data
• Programmable burst lengths: 2, 4, or 8
• Concurrent Auto Precharge option supported
• Auto Refresh and Self Refresh Modes
• ^tRAS lockout (^tRAP = ^tRCD)
OPTIONS
PART NUMBER
• Configuration
16 Meg x 8 (4 Meg x 8 x 4 banks)
16M8
• Plastic Package
66-Pin TSOP
TG
(400mil with 0.65mm pin pitch)
• Timing - Cycle Time
5ns @ CL = 3⁽¹⁾
-5
• Self Refresh
Standard
none
NOTE: 1. Supports modules with 3-4-4 timing
GENERAL DESCRIPTION
The DDR400 SDRAM is a high-speed CMOS, dy-
namic random-access memory that operates at a fre-
quency of 200 MHz (^tCK=5ns) with a peak data transfer
rate of 400Mb/s. DDR400 continues to use the JEDEC
standard SSTL_2 interface and the 2n-prefetch archi-
tecture.
The standard DDR200/DDR266 data sheets also
pertain to the DDR400 device and should be refer-
enced for a complete description of DDR SDRAM func-
tionality and operating modes. However, to meet the
faster DDR400 operating frequencies, some of the AC
timing parameters, DC levels and operating tempera-
tures are slightly tighter. This addendum data sheet
will concentrate on the key differences required to sup-
port the enhanced speeds.
The Micron 128Mb data sheet provides full specifica-
tions and functionality unless specified herein.
CONFIGURATION
Architecture
Configuration
Refresh Count
Row Addressing
Bank Addressing
Column Addressing
16 Meg x 8
4 Meg x 8 x 4 banks
4K
4K (A0–A11)
4 (BA0, BA1)
1K (A0–A9)
KEY TIMING PARAMETERS
SPEED
GRADE
-5
CLOCK RATE
CL = 3¹
200 MHz
DATA-OUT ACCESS DQS-DQ
WINDOW² WINDOW SKEW
2.15ns ±0.50ns +0.35ns
NOTE: 1. CL = CAS (Read) Latency
2. With a 50/50 clock duty cycle
128Mb: x8DDR400 SDRAM
128Mbx8DDR400.p65 – Rev. A (1/30/02-B)
1
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2002, Micron Technology, Inc.
‡_{THIS DATA SHEET CONTAINS THE PRESENT DESCRIPTION OF A PRODUCT IN DEFINITION WITH NO FORMAL DESIGN IN PROGRESS.}