GS81302D20AGD-633I Datasheet, PDF (15/26 Pages) GSI Technology – Dual Double Data Rate interface

Preliminary
GS81302D20/38AGD-633/550/500/450
AC Electrical Characteristics
Clock
Parameter
Symbol
-633
Min
Max
-550
Min
Max
-500
Min
Max
-450
Min
Max
K, K Clock Cycle Time
t_KHKH
1.58
8.4
1.81
8.4
2.0
8.4
2.2
8.4
tK Variable
t_KVar
—
0.15
—
0.15
—
0.15
—
0.15
K, K Clock High Pulse Width
t_KHKL
0.4
—
0.4
—
0.4
—
0.4
—
K, K Clock Low Pulse Width
t_KLKH
0.4
—
0.4
—
0.4
—
0.4
—
K to K High
t_KHKH
0.71
—
0.77
—
0.85
—
0.94
—
K to K High
t_KHKH
0.71
—
0.77
—
0.85
—
0.94
—
PLL Lock Time
t_KLock
20
—
20
—
20
—
20
—
K Static to PLL reset
t_KReset
30
—
30
—
30
—
30
—
K, K Clock Initialization
Output Times
t_KInit
20
—
20
—
20
—
20
—
K, K Clock High to Data Output Valid
t_KHQV
—
0.45
—
0.45
—
0.45
—
0.45
K, K Clock High to Data Output Hold
t_KHQX
–0.45
—
–0.45
—
–0.45
—
–0.45
—
K, K Clock High to Echo Clock Valid
t_KHCQV
—
0.15
—
0.29
—
0.33
—
0.37
K, K Clock High to Echo Clock Hold
t_KHCQX
–0.15
—
–0.29
—
–0.33
—
–0.37
—
CQ, CQ High Output Valid
t_CQHQV
—
0.09
—
0.15
—
0.15
—
0.15
CQ, CQ High Output Hold
t_CQHQX
–0.09
—
–0.15
—
–0.15
—
–0.15
—
CQ, CQ High to QLVD
t_QVLD
–0.15
0.15
–0.15
0.15
–0.15
0.15
–0.15
0.15
CQ Phase Distortion
t_CQHCQH
t_CQHCQH
0..57
—
0.65
—
0.75
—
0.85
—
K Clock High to Data Output High-Z
t_KHQZ
—
0.45
—
0.45
—
0.45
—
0.45
K Clock High to Data Output Low-Z
Setup Times
t_KHQX1
–0.45
—
–0.45
—
–0.45
—
–0.45
—
Address Input Setup Time
Control Input Setup Time
(RW, LD)
Control Input Setup Time
(BWX)
Data Input Setup Time
Hold Times
t_AVKH
0.23
—
0.23
—
0.25
—
0.275
—
t_IVKH
0.23
—
0.23
—
0.25
—
0.275
—
t_IVKH
0.18
—
0.18
—
0.2
—
0.22
—
t_DVKH
0.18
—
0.18
—
0.2
—
0.22
—
Address Input Hold Time
t_KHAX
0.23
—
0.23
—
0.25
—
0.275
—
Control Input Hold Time
(RW, LD)
Control Input Hold Time
(BWX)
t_KHIX
0.23
—
0.23
—
0.25
—
0.275
—
t_KHIX
0.18
—
0.18
—
0.2
—
0.22
—
Data Input Hold Time
t_KHDX
0.18
—
0.18
—
0.2
—
0.22
—
Notes:
1. All Address inputs must meet the specified setup and hold times for all latching clock edges.
2. Control signals are RW, LD.
3. Control signals are BW0, BW1 and (BW2, BW3 for x36).
4. Clock phase jitter is the variance from clock rising edge to the next expected clock rising edge.
5. V_DD slew rate must be less than 0.1 V DC per 50 ns for PLL lock retention. PLL lock time begins once V_DD and input clock are stable.
6. After device power-up, 20s of stable input clocks (as specified by t_KInit) must be supplied before reads and writes are issued.
ns
ns 4
cycle
cycle
ns
ns
s 5
ns
s 6
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns 1
ns 2
ns 3
ns
ns 1
ns 2
ns 3
ns
Rev: 1.00b 5/2017
15/26
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2017, GSI Technology