MCP19110_16 Datasheet, PDF (95/226 Pages) Microchip Technology – Digitally-Enhanced Power Analog Controller

MCP19110/11
15.3 Interrupt Control Registers
15.3.1 INTCON REGISTER
The INTCON register is a readable and writable regis-
ter, that contains the various enable and flag bits for the
TMR0 register overflow, interrupt-on-change and exter-
nal INT pin interrupts.
Note:
Interrupt flag bits are set when an interrupt
condition occurs, regardless of the state of
its corresponding enable bit or the Global
Enable bit, GIE, of the INTCON register.
User software should ensure the appropri-
ate interrupt flag bits are clear prior to
enabling an interrupt.
REGISTER 15-1: INTCON – INTERRUPT CONTROL REGISTER
R/W-0
GIE
bit 7
R/W-0
PEIE
R/W-0
T0IE
R/W-0
INTE
R/W-0
IOCE
R/W-0
T0IF
R/W-0
INTF
R/W-x
IOCF
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
Note 1:
2:
GIE: Global Interrupt Enable bit
1 = Enables all unmasked interrupts
0 = Disables all interrupts
PEIE: Peripheral Interrupt Enable bit
1 = Enables all unmasked peripheral interrupts
0 = Disables all peripheral interrupts
T0IE: TMR0 Overflow Interrupt Enable bit
1 = Enables the TMR0 interrupt
0 = Disables the TMR0 interrupt
INTE: INT External Interrupt Enable bit
1 = Enables the INT external interrupt
0 = Disables the INT external interrupt
IOCE: Interrupt-on-Change Enable bit⁽¹⁾
1 = Enables the interrupt-on-change
0 = Disables the interrupt-on-change
T0IF: TMR0 Overflow Interrupt Flag bit⁽²⁾
1 = TMR0 register has overflowed (must be cleared in software)
0 = TMR0 register did not overflow
INTF: External Interrupt Flag bit
1 = The external interrupt occurred (must be cleared in software)
0 = The external interrupt did not occur
IOCF: Interrupt-on-Change Interrupt Flag bit
1 = When at least one of the interrupt-on-change pins changed state
0 = None of the interrupt-on-change pins have changed state
IOC register must also be enabled.
T0IF bit is set when TMR0 rolls over. TMR0 is unchanged on Reset and should be initialized before clear-
ing T0IF bit.
 2013-2016 Microchip Technology Inc.
DS20002331D-page 95