PIC16C7X Datasheet, PDF (94/288 Pages) Microchip Technology – 8-Bit CMOS Microcontrollers with A/D Converter

PIC16C7X
Applicable Devices
72 73 73A 74 74A 76 77
11.5.1 SLAVE MODE
In slave mode, the SCL and SDA pins must be config-
ured as inputs (TRISC<4:3> set). The SSP module will
override the input state with the output data when
required (slave-transmitter).
When an address is matched or the data transfer after
an address match is received, the hardware automati-
cally will generate the acknowledge (ACK) pulse, and
then load the SSPBUF register with the received value
currently in the SSPSR register.
There are certain conditions that will cause the SSP
module not to give this ACK pulse. These are if either
(or both):
a) The buffer full bit BF (SSPSTAT<0>) was set
before the transfer was received.
b) The overflow bit SSPOV (SSPCON<6>) was set
before the transfer was received.
In this case, the SSPSR register value is not loaded
into the SSPBUF, but bit SSPIF (PIR1<3>) is set.
Table 11-4 shows what happens when a data transfer
byte is received, given the status of bits BF and SSPOV.
The shaded cells show the condition where user soft-
ware did not properly clear the overflow condition. Flag
bit BF is cleared by reading the SSPBUF register while
bit SSPOV is cleared through software.
The SCL clock input must have a minimum high and
low for proper operation. The high and low times of the
I²C specification as well as the requirement of the SSP
module is shown in timing parameter #100 and param-
eter #101.
11.5.1.1 ADDRESSING
Once the SSP module has been enabled, it waits for a
START condition to occur. Following the START condi-
tion, the 8-bits are shifted into the SSPSR register. All
incoming bits are sampled with the rising edge of the
clock (SCL) line. The value of register SSPSR<7:1> is
compared to the value of the SSPADD register. The
address is compared on the falling edge of the eighth
clock (SCL) pulse. If the addresses match, and the BF
and SSPOV bits are clear, the following events occur:
a) The SSPSR register value is loaded into the
SSPBUF register.
b) The buffer full bit, BF is set.
c) An ACK pulse is generated.
d) SSP interrupt flag bit, SSPIF (PIR1<3>) is set
(interrupt is generated if enabled) - on the falling
edge of the ninth SCL pulse.
In 10-bit address mode, two address bytes need to be
received by the slave (Figure 11-16). The five Most Sig-
nificant bits (MSbs) of the first address byte specify if
this is a 10-bit address. Bit R/W (SSPSTAT<2>) must
specify a write so the slave device will receive the sec-
ond address byte. For a 10-bit address the first byte
would equal ‘1111 0 A9 A8 0’, where A9 and A8 are
the two MSbs of the address. The sequence of events
for 10-bit address is as follows, with steps 7- 9 for
slave-transmitter:
1. Receive first (high) byte of Address (bits SSPIF,
BF, and bit UA (SSPSTAT<1>) are set).
2. Update the SSPADD register with second (low)
byte of Address (clears bit UA and releases the
SCL line).
3. Read the SSPBUF register (clears bit BF) and
clear flag bit SSPIF.
4. Receive second (low) byte of Address (bits
SSPIF, BF, and UA are set).
5. Update the SSPADD register with the first (high)
byte of Address, if match releases SCL line, this
will clear bit UA.
6. Read the SSPBUF register (clears bit BF) and
clear flag bit SSPIF.
7. Receive repeated START condition.
8. Receive first (high) byte of Address (bits SSPIF
and BF are set).
9. Read the SSPBUF register (clears bit BF) and
clear flag bit SSPIF.
TABLE 11-4: DATA TRANSFER RECEIVED BYTE ACTIONS
Status Bits as Data
Transfer is Received
BF
SSPOV
0
0
1
0
1
1
0
1
SSPSR → SSPBUF
Yes
No
No
No
Generate ACK
Pulse
Yes
No
No
No
Set bit SSPIF
(SSP Interrupt occurs
if enabled)
Yes
Yes
Yes
Yes
DS30390E-page 94
© 1997 Microchip Technology Inc.