MCP37210-200 Datasheet, PDF (92/116 Pages) Microchip Technology – Output Data Format

MCP37210-200 AND MCP37D10-200
REGISTER 5-58: ADDRESS 0X94 – NCO PHASE OFFSET (REPEAT) IN DDC MODE (LOWER BYTE)⁽¹⁾
R/W-0
bit 7
R/W-0
R/W-0
R/W-0
R/W-0
NCO_PHASE<7:0>
R/W-0
R/W-0
R/W-0
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
bit 7-0
Note 1:
NCO_PHASE<7:0>: Lower byte of NCO_PHASE<15:0>⁽¹⁾
0000-0000 = 0° when NCO_PHASE<15:0> = 0x0000 (Default)
See Note 1 in Register 5-44. Keep this register setting the same as in Address 0x86.
REGISTER 5-59: ADDRESS 0X95 – NCO PHASE OFFSET (REPEAT) IN DDC MODE (UPPER BYTE)⁽¹⁾
R/W-0
bit 7
R/W-0
R/W-0
R/W-0
R/W-0
NCO_PHASE<15:8>
R/W-0
R/W-0
R/W-0
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
bit 7-0
Note 1:
NCO_PHASE<15:8>: Upper byte of NCO_PHASE<15:0>⁽¹⁾
0000-0000 = 0° when NCO_PHASE<15:0> = 0x0000 (Default)
See Note 1 in Register 5-44. Keep this register setting the same as in Address 0x87.
DS20005395B-page 92
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