MCP6244 Datasheet, PDF (9/28 Pages) Microchip Technology – 50 uA, 550 kHz Rail-to-Rail Op Amp

1.E+1004k
1.E+013k
G_N = +1 V/V
G_N t +2 V/V
1.E+10020
1.¹E⁰+^p01
1¹.E⁰+⁰0^p2
1.E¹+ⁿ03
1.¹E⁰+ⁿ04
Normalized Load Capacitance; C_L/G_N (F)
FIGURE 4-4:
Recommended R_ISO Values
for Capacitive Loads.
After selecting R_ISO for your circuit, double-check the
resulting frequency response peaking and step
response overshoot. Evaluation on the bench and
simulations with the MCP6241/2/4 SPICE macro
model are very helpful. Modify R_ISO’s value until the
response is reasonable.
4.4 Supply Bypass
With this op amp, the power supply pin (V_DD for
single-supply) should have a local bypass capacitor
(i.e., 0.01 µF to 0.1 µF) within 2 mm for good high-
frequency performance. It can use a bulk capacitor
(i.e., 1 µF or larger) within 100 mm to provide large,
slow currents. This bulk capacitor can be shared with
other nearby analog parts.
4.5 Unused Op Amps
An unused op amp in a quad package (MCP6244)
should be configured as shown in Figure 4-5. Both
circuits prevent the output from toggling and causing
crosstalk. Circuit A can use any reference voltage
between the supplies, provides a buffered DC voltage,
and minimizes the supply current draw of the unused
op amp. Circuit B minimizes the number of
components, but may draw a little more supply current
for the unused op amp.
¼ MCP6244 (A)
V_DD
V_DD
¼ MCP6244 (B)
V_DD
MCP6241/2/4
4.6 PCB Surface Leakage
In applications where low input bias current is critical,
PCB (printed circuit board) surface leakage effects
need to be considered. Surface leakage is caused by
humidity, dust or other contamination on the board.
Under low humidity conditions, a typical resistance
between nearby traces is 10¹²Î©. A 5V difference would
cause 5 pA of current to flow, which is greater than the
MCP6241/2/4 family’s bias current at 25°C (1 pA, typ.).
The easiest way to reduce surface leakage is to use a
guard ring around sensitive pins (or traces). The guard
ring is biased at the same voltage as the sensitive pin.
An example of this type of layout is shown in
Figure 4-6.
V_IN-
V_IN+
V_SS
Guard Ring
FIGURE 4-6:
Example Guard Ring Layout
for Inverting Gain.
1. Non-inverting Gain and Unity-Gain Buffer:
a. Connect the non-inverting pin (V_IN+) to the
input with a wire that does not touch the
PCB surface.
b. Connect the guard ring to the inverting input
pin (V_IN–). This biases the guard ring to the
common mode input voltage.
2. Inverting Gain and Transimpedance Amplifiers
(convert current to voltage, such as photo
detectors):
a. Connect the guard ring to the non-inverting
input pin (V_IN+). This biases the guard ring
to the same reference voltage as the op
amp (e.g., V_DD/2 or ground).
b. Connect the inverting pin (V_IN–) to the input
with a wire that does not touch the PCB
surface.
FIGURE 4-5:
Unused Op Amps.
© 2005 Microchip Technology Inc.
DS21882C-page 9