93LCS56_04 Datasheet, PDF (9/14 Pages) Microchip Technology – 2K/4K 2.5V Microwire Serial EEPROM with Software Write Protect

FIGURE 2-10: PREN TIMING
93LCS56/66
PRE
PE
CS
CLK
T CSL
DI
1
0
0
1
1
X
†††
X
DO = TRI-STATE
A EWEN cycle must precede a PREN cycle.
6 DON'T CARE BITS
FIGURE 2-11: PRCLEAR TIMING
PRE
PE
CS
CLK
TCSL
DI
1
1
1
1 •••
1
1
1
1
8 BITS OF "1"
TRI-STATE
DO
A PREN cycle must immediately precede a PRCLEAR cycle.
FIGURE 2-12: PRWRITE TIMING
PRE
BUSY
TWC
READY
PE
CS
CLK
TCSL
DI
1
0
1
A7 • • •
A0
DO
BUSY
TWC
Protect Register MUST be cleared before a PRWRITE cycle.
A PREN cycle must immediately precede a PRWRITE cycle.
Address bit A7 is a "don't care" for 93LCS56.
READY
 2004 Microchip Technology Inc.
DS11181E-page 9