24LC128 Datasheet, PDF (9/38 Pages) Microchip Technology – 128K I2C™ CMOS Serial EEPROM

24AA128/24LC128/24FC128
FIGURE 6-1:
BYTE WRITE
Bus Activity
Master
SDA Line
S
T
A
R
Control
Byte
T
S
1
0
1
0
A
2
A
1
A
0
0
Address
High Byte
xx
Address
Low Byte
S
T
Data
O
P
P
Bus Activity
A
A
A
A
C
C
C
C
K
K
K
K
x = “don’t care” bit
FIGURE 6-2:
PAGE WRITE
S
Bus Activity
Master
T
A
R
Control
Byte
T
Address
High Byte
Address
Low Byte
SDA Line
S
1
0
1
0
A
2
A
1
A
0
0
xx
Bus Activity
A
A
C
C
K
K
x = “don’t care” bit
Data Byte 0
A
A
C
C
K
K
S
Data Byte 63
T
O
P
P
A
C
K
7.0 ACKNOWLEDGE POLLING
Since the device will not acknowledge during a write
cycle, this can be used to determine when the cycle is
complete (This feature can be used to maximize bus
throughput). Once the Stop condition for a Write
command has been issued from the master, the device
initiates the internally timed write cycle. ACK polling
can be initiated immediately. This involves the master
sending a Start condition, followed by the control byte
for a Write command (R/W = 0). If the device is still
busy with the write cycle, then no ACK will be returned.
If no ACK is returned, the Start bit and control byte must
be resent. If the cycle is complete, then the device will
return the ACK and the master can then proceed with
the next Read or Write command. See Figure 7-1 for
flow diagram.
FIGURE 7-1:
ACKNOWLEDGE
POLLING FLOW
Send
Write Command
Send Stop
Condition to
Initiate Write Cycle
Send Start
Send Control Byte
with R/W = 0
Did Device
No
Acknowledge
(ACK = 0)?
Yes
Next
Operation
 2010 Microchip Technology Inc.
DS21191S-page 9