24AA014H Datasheet, PDF (9/28 Pages) Microchip Technology – 1K I2C™ Serial EEPROM with Half-Array Write-Protect

24AA014H/24LC014H
6.0 WRITE OPERATIONS
6.1 Byte Write
Following the Start signal from the master, the device
code(4 bits), the Chip Select bits (3 bits) and the R/W
bit (which is a logic low) are placed onto the bus by the
master transmitter. The device will acknowledge this
control byte during the ninth clock pulse. The next byte
transmitted by the master is the word address and will
be written into the Address Pointer of the 24AA014H/
24LC014H. After receiving another Acknowledge
signal from the 24AA014H/24LC014H, the master
device will transmit the data word to be written into the
addressed memory location. The 24AA014H/
24LC014H acknowledges again and the master
generates a Stop condition. This initiates the internal
write cycle and the 24AA014H/24LC014H will not
generate Acknowledge signals during this time
(Figure 6-1). If an attempt is made to write to the
protected portion of the array when the hardware write
protection has been enabled, the device will
acknowledge the command, but no data will be written.
The write cycle time must be observed even if write
protection is enabled.
6.2 Page Write
The write-control byte, word address and the first data
byte are transmitted to the 24AA014H/24LC014H in the
same way as in a byte write. But instead of generating
a Stop condition, the master transmits up to 15
additional data bytes to the 24AA014H/24LC014H that
are temporarily stored in the on-chip page buffer and
will be written into the memory once the master has
transmitted a Stop condition. Upon receipt of each
word, the four lower order Address Pointer bits are
internally incremented by one.
The higher order four bits of the word address remain
constant. If the master should transmit more than 16
bytes prior to generating the Stop condition, the
address counter will roll over and the previously
received data will be overwritten. As with the byte write
operation, once the Stop condition is received, an
internal write cycle will begin (Figure 6-2). If an attempt
is made to write to the protected portion of the array
when the hardware write protection has been enabled,
the device will acknowledge the command, but no data
will be written. The write cycle time must be observed
even if write protection is enabled.
Note:
Page write operations are limited to writing
bytes within a single physical page,
regardless of the number of bytes
actually being written. Physical page
boundaries start at addresses that are
integer multiples of the page buffer size (or
‘page size’) and end at addresses that are
integer multiples of [page size – 1]. If a
Page Write command attempts to write
across a physical page boundary, the
result is that the data wraps around to the
beginning of the current page (overwriting
data previously stored there), instead of
being written to the next page, as might be
expected. It is therefore necessary that the
application software prevent page write
operations that would attempt to cross a
page boundary.
6.3 Write Protection
The WP pin must be tied to VCC or VSS. If tied to VCC,
half of the array will be write-protected (40h-7Fh). If the
WP pin is tied to VSS, write operations to all address
locations are allowed.
FIGURE 6-1:
BYTE WRITE
S
Bus Activity
T
A
Master
R
T
Control
Byte
SDA Line
S
Word
Address
Bus Activity
A
A
C
C
K
K
Data
S
T
O
P
P
A
C
K
FIGURE 6-2:
Bus Activity
Master
SDA Line
Bus Activity
PAGE WRITE
S
T
A
Control
R
Byte
T
Word
Address (n)
S
A
A
C
C
K
K
Data (n)
Data (n +1)
A
A
C
C
K
K
S
T
Data (n + 15)
O
P
P
A
C
K
© 2008 Microchip Technology Inc.
Preliminary
DS22077B-page 9