DSPIC33FJ128GP306AT-IPT Datasheet, PDF (86/362 Pages) Microchip Technology – 16-bit Digital Signal Controllers (up to 256 KB Flash and 30 KB SRAM) with Advanced Analog

dsPIC33FJXXXGPX06A/X08A/X10A
TABLE 6-1: RESET FLAG BIT OPERATION
Flag Bit
Setting Event
TRAPR (RCON<15>)
Trap conflict event
IOPUWR (RCON<14>)
Illegal opcode or uninitialized
W register access
EXTR (RCON<7>)
MCLR Reset
SWR (RCON<6>)
RESET instruction
WDTO (RCON<4>)
WDT time-out
SLEEP (RCON<3>)
PWRSAV #SLEEP instruction
IDLE (RCON<2>)
PWRSAV #IDLE instruction
BOR (RCON<1>)
BOR, POR
POR (RCON<0>)
POR
Note: All Reset flag bits may be set or cleared by the user software.
Clearing Event
POR, BOR
POR, BOR
POR
POR, BOR
PWRSAV instruction, POR, BOR
POR, BOR
POR, BOR
—
—
6.1 Clock Source Selection at Reset
If clock switching is enabled, the system clock source at
device Reset is chosen, as shown in Table 6-2. If clock
switching is disabled, the system clock source is always
selected according to the oscillator Configuration bits.
Refer to Section 9.0 “Oscillator Configuration” for
further details.
TABLE 6-2:
Reset Type
POR
BOR
MCLR
WDTR
SWR
OSCILLATOR SELECTION VS
TYPE OF RESET (CLOCK
SWITCHING ENABLED)
Clock Source Determinant
Oscillator Configuration bits
(FNOSC<2:0>)
COSC Control bits
(OSCCON<14:12>)
6.2 Device Reset Times
The Reset times for various types of device Reset are
summarized in Table 6-3. The system Reset signal,
SYSRST, is released after the POR and PWRT delay
times expire.
The time at which the device actually begins to execute
code also depends on the system oscillator delays,
which include the Oscillator Start-up Timer (OST) and
the PLL lock time. The OST and PLL lock times occur
in parallel with the applicable SYSRST delay times.
The FSCM delay determines the time at which the
FSCM begins to monitor the system clock source after
the SYSRST signal is released.
DS70593D-page 86
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