93AA46A_05 Datasheet, PDF (8/28 Pages) Microchip Technology – 1K Microwire Compatible Serial EEPROM

93AA46A/B/C, 93LC46A/B/C, 93C46A/B/C
2.5 Erase All (ERAL)
The Erase All (ERAL) instruction will erase the entire
memory array to the logical ‘1’ state. The ERAL cycle
is identical to the erase cycle, except for the different
opcode. The ERAL cycle is completely self-timed and
commences at the falling edge of the CS, except on
‘93C’ devices where the rising edge of CLK before the
last data bit initiates the write cycle. Clocking of the
CLK pin is not necessary after the device has entered
the ERAL cycle.
The DO pin indicates the Ready/Busy status of the
device, if CS is brought high after a minimum of 250 ns
low (TCSL).
Note:
After the ERAL command is complete,
issuing a Start bit and then taking CS low
will clear the Ready/Busy status from DO.
VCC must be ≥ 4.5V for proper operation of ERAL.
FIGURE 2-3:
CS
ERAL TIMING FOR 93AA AND 93LC DEVICES
TCSL
Check Status
CLK
DI
1
00
10
x •••
x
High-Z
DO
VCC must be ≥ 4.5V for proper operation of ERAL.
TSV
Busy
TEC
TCZ
Ready
High-Z
FIGURE 2-4:
CS
ERAL TIMING FOR 93C DEVICES
TCSL
Check Status
CLK
DI
1
00
10
x •••
x
High-Z
DO
TSV
Busy
TEC
TCZ
Ready
High-Z
DS21749F-page 8
© 2005 Microchip Technology Inc.