24LC21A-I Datasheet, PDF (8/18 Pages) Microchip Technology – 1K 2.5V Dual Mode I2C Serial EEPROM

24LC21A
FIGURE 3-5:
BUS TIMING START/STOP
SCL
SDA
TSU:STA
THD:STA
VHYS
TSU:STO
START
STOP
FIGURE 3-6:
BUS TIMING DATA
TF
TLOW
THIGH
SCL
TSU:STA
THD:STA
THD:DAT
SDA
IN
TSP
TAA
TAA
SDA
OUT
TR
TSU:DAT _TSU:STO
TBUF
3.1.6 SLAVE ADDRESS
After generating a Start condition, the bus master
transmits the slave address consisting of a 7-bit device
code (1010000) for the 24LC21A.
The eighth bit of slave address determines whether the
master device wants to read or write to the 24LC21A
(Figure 3-7).
The 24LC21A monitors the bus for its corresponding
slave address continuously. It generates an
Acknowledge bit if the slave address was true and it is
not in a programming mode.
Operation
Slave Address
R/W
Read
1010000
1
Write
1010000
0
FIGURE 3-7:
START
CONTROL BYTE
ALLOCATION
READ/WRITE
SLAVE ADDRESS
R/W A
1
0
1
0
0
0
0
DS21160F-page 8
 2003 Microchip Technology Inc.