24LC164 Datasheet, PDF (8/16 Pages) Microchip Technology – 16K 2.5V Cascadable I2C™ Serial EEPROM

24LC164
FIGURE 7-1:
CURRENT ADDRESS READ
BUS ACTIVITY
MASTER
S
T
A
R
CONTROL
BYTE
T
SDA LINE
S 1 A2A1A0B2B1B0
S
T
DATA (n)
O
P
P
A
BUS ACTIVITY
C
K
FIGURE 7-2:
RANDOM READ
S
T
BUS ACTIVITY
MASTER
A
R
T
CONTROL
BYTE
SDA LINE
S 1 A2 A1A0B2B1B0
A
C
BUS ACTIVITY
K
WORD
ADDRESS (n)
S
T
A
R
T
S
A
C
K
CONTROL
BYTE
N
O
A
C
K
S
T
DATA (n)
O
P
P
A
N
C
O
K
A
C
K
FIGURE 7-3:
SEQUENTIAL READ
BUS ACTIVITY CONTROL
MASTER
BYTE
DATA (n)
DATA (n + 1)
DATA (n + 2)
S
T
O
DATA (n + X)
P
SDA LINE
P
A
A
A
A
N
BUS ACTIVITY
C
C
C
C
O
K
K
K
K
A
C
K
8.0 PIN DESCRIPTIONS
8.1 SDA Serial Address/Data Input/
Output
This is a bi-directional pin used to transfer addresses
and data into and data out of the device. It is an open
drain terminal. Therefore, the SDA bus requires a pul-
lup resistor to VCC (typical 10kΩ for 100 kHz, 2kΩ for
400 kHz).
For normal data transfer SDA is allowed to change only
during SCL LOW. Changes during SCL HIGH are
reserved for indicating the START and STOP condi-
tions.
8.2 SCL Serial Clock
This input is used to synchronize the data transfer from
and to the device.
8.3 WP
This pin must be connected to either VSS or VCC.
If tied to VSS, normal memory operation is enabled
(read/write the entire memory 000-7FF).
If tied to VCC, WRITE operations are inhibited. The
entire memory will be write-protected. Read operations
are not affected.
This feature allows the user to use the 24LC164 as a
serial ROM when WP is enabled (tied to VCC).
8.4 A0, A1, A2
These pins are used to configure the proper chip
address in multiple-chip applications (more than one
24LC164 on the same bus). The levels on these pins
are compared to the corresponding bits in the slave
address. The chip is selected if the compare is true.
Note: The level on A1 is compared to the
inverse of the slave address.
Up to eight 24LC164s may be connected to the same
bus. These pins must be connected to either VSS or
VCC.
DS21093I-page 8
 2004 Microchip Technology Inc.