24AA1026_12 Datasheet, PDF (8/28 Pages) Microchip Technology – 1024K I2C™ Serial EEPROM

24AA1026/24LC1026/24FC1026
5.0 DEVICE ADDRESSING
A control byte is the first byte received following the
Start condition from the master device (Figure 5-1).
The control byte consists of a 4-bit control code; for the
24XX1026, this is set as ‘1010’ binary for read and
write operations. The next two bits of the control byte
are the Chip Select bits (A2, A1). The Chip Select bits
allow the use of up to four 24XX1026 devices on the
same bus and are used to select which device is
accessed. The Chip Select bits in the control byte must
correspond to the logic levels on the corresponding A2
and A1 pins for the device to respond. These bits are in
effect the two Most Significant bits (MSb) of the word
address. The next bit of the control byte is the block
select bit (B0). This bit acts as the A16 address bit for
accessing the entire array.
The last bit of the control byte defines the operation to
be performed. When set to a one, a read operation is
selected, and when set to a zero, a write operation is
selected. The next two bytes received define the
address of the first data byte (Figure 5-2). The upper
address bits are transferred first, followed by the Least
Significant bits (LSb).
Following the Start condition, the 24XX1026 monitors
the SDA bus checking the device type identifier being
transmitted. Upon receiving a ‘1010’ code and
appropriate device select bits, the slave device outputs
an Acknowledge signal on the SDA line. Depending on
the state of the R/W bit, the 24XX1026 will select a read
or write operation.
This device has an internal addressing boundary
limitation that is divided into two segments of 512K bits.
Block select bit ‘B0’ is used to control access to each
segment.
FIGURE 5-1:
CONTROL BYTE
FORMAT
Control Code
Read/Write Bit
Chip Block
Select Select
Bits Bit
S 1 0 1 0 A2 A1 B0 R/W ACK
Start Bit
Slave Address
Acknowledge Bit
5.1 Contiguous Addressing Across
Multiple Devices
The Chip Select bits A2 and A1 can be used to expand
the contiguous address space for up to 4 Mbit by add-
ing up to four 24XX1026’s on the same bus. In this
case, software can use A1 of the control byte as
address bit A17 and A2 as address bit A18. It is not
possible to sequentially read across device boundar-
ies.
Each device has internal addressing boundary
limitations. This divides each part into two segments of
512K bits. The block select bit ‘B0’ controls access to
each “half”.
Sequential read operations are limited to 512K blocks.
To read through four devices on the same bus, eight
random Read commands must be given.
FIGURE 5-2:
ADDRESS SEQUENCE BIT ASSIGNMENTS
Control Byte
Address High Byte
Address Low Byte
1
0
1
0
A
2
A
1
B
0
R/W
Control
Code
Chip Block
Select Select
Bits Bit
A A A AA A A A
15 14 13 12 11 10 9 8
A
7
•
•
•
•
•
•
A
0
DS22270C-page 8
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