PIC14000 Datasheet, PDF (79/153 Pages) Microchip Technology – 28-Pin Programmable Mixed Signal Controller

PIC14000
TABLE 10-3: STATUS BITS AND THEIR SIGNIFICANCE
POR
TO
PD
Meaning
0
1
1
Power-On Reset
0
0
X
Illegal, TO is set on POR
0
X
0
Illegal, PD is set on POR
1
0
1
WDT reset during normal operation
1
0
0
WDT time-out wakeup from sleep
1
1
1
MCLR reset during normal operation
1
1
0
MCLR reset during SLEEP or HIBERNATE, or interrupt wake-up from
SLEEP or HIBERNATE.
10.4 Low-Voltage Detector
The PIC14000 contains an integrated low-voltage
detector. The supply voltage is divided and compared
to the bandgap reference output. If the supply voltage
(VDD) falls below VTRIP-, then the low-voltage detector
will cause LVD (PCON<0>) to be reset. This bit can be
read by software to determine if a low voltage condition
occurred. This bit must be set by software.
The nominal values of the low-voltage detector trip
points are as follows:
• VTRIP- = 2.55V
• VTRIP+ = 2.60V
• Hysteresis (VTRIP+ – VTRIP-) = 55 mV
10.5 Power-on Reset (POR), Power-up
Timer (PWRT) and Oscillator Start-up
Timer (OST)
10.5.1 POWER-ON RESET (POR)
A Power-on Reset pulse is generated on-chip when
VDD rise is detected (in the range of 1.5V - 2.1V). To
take advantage of the POR, just tie the MCLR pin
directly (or through a resistor) to VDD. This will elimi-
nate external RC components usually needed to create
a Power-on Reset. A maximum rise time for VDD is
specified. See Electrical Specifications for details.
When the device starts normal operation (exits the
reset condition), device operating parameters (voltage,
frequency, temperature, ...) must be met to ensure
operation. If these conditions are not met, the device
must be held in reset until the operating conditions are
met.
For additional information, refer to Application Note
AN607, “Power-up Trouble Shooting.”
10.5.2 POWER-UP TIMER (PWRT)
The Power-up Timer provides a fixed 72 ms (nominal)
time-out on power-up only, from POR. The power-up
timer operates from a local internal oscillator. The chip
is kept in reset as long as PWRT is active. The PWRT
delay allows the VDD to rise to an acceptable level. A
configuration bit, PWRTE, can disable (if set, or unpro-
grammed) or enable (if cleared, or programmed) the
power-up timer.
The power-up timer delay will vary from chip to chip
and due to VDD and temperature.
10.5.3 OSCILLATOR START-UP TIMER (OST)
The Oscillator Start-up Timer (OST) provides 1024
oscillator cycles (from OSC1 input) delay after the
PWRT delay is over. This guarantees that the crystal
oscillator or resonator has started and stabilized.
10.5.4 IN OSCILLATOR START-UP
There is an 8-cycle delay in IN mode to ensure stability
only after a Power-on Reset (POR) or wake-up from
SLEEP.
© 1996 Microchip Technology Inc.
Preliminary
DS40122B-page 79