JS28F128P33TF70A Datasheet, PDF (76/88 Pages) Microchip Technology – 128-Mbit, 64-Mbit Single Bit per Cell (SBC)

P33-65nm
Figure 33: BEFP Flowchart
Setup Phase
Start
A
Issue BEFP Setup Cmd
(Data = 0x80)
Issue BEFP Confirm Cmd
(Data = 00D0h)
BEFP
Setup
Delay
Read Status
Register
BEFP Setup
Done ?
Yes (SR.7=0)
A
No (SR.7=1)
SR Error Handler
(User-Defined)
Exit
Program/Verify Phase
Read Status
Register
B
No (SR.0=1)
Buffer Ready ?
Yes (SR.0=0)
Write Data Word to Buffer
Buffer Full ?
No
Yes
Read Status
Register
No (SR.0=1)
Program
Done ?
Yes (SR.0=0)
Yes
Program
More Data ?
No
Write 0xFFFFh outside Block
B
Exit Phase
Read Status
Register
No (SR.7=0)
BEFP Exited ?
Yes (SR.7=1)
Full Status
Register check for
errors
Finish
Datasheet
76
Jul 2011
Order Number: 208034-04