DSPIC33FJXXXMCX06A Datasheet, PDF (76/352 Pages) Microchip Technology – High-Performance, 16-bit Digital Signal Controllers

dsPIC33FJXXXMCX06A/X08A/X10A
5.2 RTSP Operation
The dsPIC33FJXXXMCX06A/X08A/X10A Flash
program memory array is organized into rows of
64 instructions or 192 bytes. RTSP allows the user to
erase a page of memory at a time, which consists of
eight rows (512 instructions), and to program one row
or one word at a time. Table 26-12 shows typical erase
and programming times. The 8-row erase pages and
single row write rows are edge-aligned, from the begin-
ning of program memory, on boundaries of 1536 bytes
and 192 bytes, respectively.
The program memory implements holding buffers that
can contain 64 instructions of programming data. Prior
to the actual programming operation, the write data
must be loaded into the buffers in sequential order. The
instruction words loaded must always be from a group
of 64 boundaries.
The basic sequence for RTSP programming is to set up
a Table Pointer, then do a series of TBLWT instructions
to load the buffers. Programming is performed by
setting the control bits in the NVMCON register. A total
of 64 TBLWTL and TBLWTH instructions are required
to load the instructions.
All of the table write operations are single-word writes
(two instruction cycles), because only the buffers are
written. A programming cycle is required for
programming each row.
5.3 Programming Operations
A complete programming sequence is necessary for
programming or erasing the internal Flash in RTSP
mode. The processor stalls (waits) until the
programming operation is finished.
The programming time depends on the FRC accuracy
(see Table 26-19) and the value of the FRC Oscillator
Tuning register (see Register 9-4). Use the following
formula to calculate the minimum and maximum values
for the row write time, page erase time and word write
cycle time parameters (see Table 26-12).
EQUATION 5-1: PROGRAMMING TIME
7----.-3---7-----M^-----H^----z^----^-----^--F^----R^----C^-----A^----c^--c^---u^---r^--Ta---c^---y^---^---%------^-----^--F^----R^----C^-----T^---u^----n^---i^-n^---g^----^--%---
For example, if the device is operating at +125°C,
the FRC accuracy will be ±5%. If the TUN<5:0> bits
(see Register 9-4) are set to ‘b111111, the
minimum row write time is:
T_RW = _{7----.-3---7-----M}-----_H----_z----_-----_-¹-1--¹---⁰₊---⁶--0-⁴--.-0-^C--5--^y--_-^c--_-^l-^e---^s_--1-----_–----0---.--0---0---3---7---5----_= 1.435ms
and the maximum row write time is:
T_RW = _{7---.--3---7-----M}-----_H----_z----_-----_¹--1--¹--⁰-_–---⁶-0-⁴--.--0-^C--5--^y-_--^c--_^l--^e---_^s--1-----_–----0---.-0----0--3---7----5---_ = 1.586ms
Setting the WR bit (NVMCON<15>) starts the operation
and the WR bit is automatically cleared when the
operation is finished.
5.4 Control Registers
There are two SFRs used to read and write the
program Flash memory: NVMCON and NVMKEY.
The NVMCON register (Register 5-1) controls which
blocks are to be erased, which memory type is to be
programmed and the start of the programming cycle.
NVMKEY is a write-only register that is used for write
protection. To start a programming or erase sequence,
the user must consecutively write 0x55 and 0xAA to the
NVMKEY register. Refer to Section 5.3 “Programming
Operations” for further details.
DS70594B-page 76
Preliminary
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