93AA46A_05 Datasheet, PDF (7/28 Pages) Microchip Technology – 1K Microwire Compatible Serial EEPROM

93AA46A/B/C, 93LC46A/B/C, 93C46A/B/C
2.4 Erase
The ERASE instruction forces all data bits of the
specified address to the logical ‘1’ state. CS is brought
low following the loading of the last address bit. This
falling edge of the CS pin initiates the self-timed
programming cycle, except on ‘93C’ devices where the
rising edge of CLK before the last address bit initiates
the write cycle.
The DO pin indicates the Ready/Busy status of the
device if CS is brought high after a minimum of 250 ns
low (TCSL). DO at logical ‘0’ indicates that programming
is still in progress. DO at logical ‘1’ indicates that the
register at the specified address has been erased and
the device is ready for another instruction.
Note:
After the Erase cycle is complete, issuing
a Start bit and then taking CS low will clear
the Ready/Busy status from DO.
FIGURE 2-1:
CS
ERASE TIMING FOR 93AA AND 93LC DEVICES
TCSL
Check Status
CLK
DI
1
1
1 AN AN-1 AN-2 ••• A0
High-Z
DO
TSV
Busy
TWC
TCZ
Ready
High-Z
FIGURE 2-2:
CS
ERASE TIMING FOR 93C DEVICES
TCSL
Check Status
CLK
DI
1
1
1 AN AN-1 AN-2 ••• A0
High-Z
DO
TSV
Busy
TWC
TCZ
Ready
High-Z
© 2005 Microchip Technology Inc.
DS21749F-page 7