59C11 Datasheet, PDF (7/12 Pages) Microchip Technology – 1K 5.0V Microwire Serial EEPROM

3.0 PIN DESCRIPTION
3.1 Chip Select (CS)
A HIGH level selects the device. A LOW level dese-
lects the device and forces it into standby mode. How-
ever, a WRITE cycle which is already initiated and/or in
progress will be completed, regardless of the CS input
signal. If CS is brought LOW during a WRITE cycle, the
device will go into standby mode as soon as the WRITE
cycle is completed.
CS must be LOW for 100 ns (TCSL) minimum between
consecutive instructions. If CS is LOW, the internal
control logic is held in a RESET status.
3.2 Serial Clock (CLK)
The Serial Clock is used to synchronize the communi-
cation between a master device and the 59C11.
Opcode, address, and data bits are clocked in on the
positive edge of CLK. Data bits are also clocked out on
the positive edge of CLK.
CLK can be stopped anywhere in the transmission
sequence (at HIGH or LOW level) and can be continued
anytime (with respect to clock high time (TCKH) and
clock low time (TCKL)). This gives freedom in preparing
opcode, address and data for the controlling master.
CLK is a “Don't Care” if CS is LOW (device deselected).
If CS is HIGH, but a START condition has not been
detected, any number of clock cycles can be received
by the device without changing its status (i.e., waiting
for START condition).
CLK cycles are not required during the self-timed
WRITE (i.e., auto erase/write) cycle.
After detection of a START condition the specified num-
ber of clock cycles (respectively LOW to HIGH transi-
tions of CLK) must be provided. These clock cycles are
required to clock in all required opcode, address, and
data bits before an instruction is executed (see instruc-
tion set truth table). When that limit has been reached,
CLK and DI become “Don't Care” inputs until CS is
brought LOW for at least chip select low time (TCSL)
and brought HIGH again and a WRITE cycle (if any) is
completed.
3.3 Data In (DI)
Data In is used to clock in START bit, opcode, address
and data synchronously with the CLK input.
59C11
3.4 Data Out (DO)
Data Out is used in the READ mode to output data syn-
chronously with the CLK input (TPD after the positive
edge of CLK). This output is in HIGH–Z mode except
if data is clocked out as a result of a READ instruction.
DI and DO can be connected together to perform a 3-
wire interface (CS, CLK, DI/DO).
Care must be taken with the leading dummy zero which
is output after a READ command has been detected.
Also, the controlling device must not drive the DI/DO
bus during WRITE cycles.
3.5 Organization (ORG)
This input selects the memory array organization.
When the ORG pin is connected to +5 V the 64 x 16
organization is selected. When it is connected to
ground, the 128 x 8 organization is selected. If the
ORG pin is left unconnected, then an internal pull-up
device will select the 64 x 16 organization. In applica-
tions subject to electrical noise, it is recommended that
this pin not be left floating, but tied either high or low.
3.6 Ready/Busy (RDY/BSY)
Pin 7 provides RDY/BSY status information. RDY/BSY
is low if the device is performing a WRITE, ERAL, or
WRAL operation. When it is HIGH the internal, self-
timed WRITE, ERAL or WRAL operation has been
completed and the device is ready to receive a new
instruction.
© 1996 Microchip Technology Inc.
DS20040J-page 7