24AA64FT-I Datasheet, PDF (7/30 Pages) Microchip Technology – 64K I2C Serial EEPROM with Quarter-Array Write-Protect

24AA64F/24LC64F
5.0 DEVICE ADDRESSING
A control byte is the first byte received following the
Start condition from the master device (Figure 5-1).
The control byte consists of a four-bit control code. For
the 24XX64F, this is set as ‘1010’ binary for read and
write operations. The next three bits of the control byte
are the Chip Select bits (A2, A1, A0). The Chip Select
bits allow the use of up to eight 24XX64F devices on
the same bus and are used to select which device is
accessed. The Chip Select bits in the control byte must
correspond to the logic levels on the corresponding A2,
A1 and A0 pins for the device to respond. These bits
are, in effect, the three Most Significant bits of the word
address.
For the SOT-23 package, the address pins are not
available. During device addressing, the A2, A1 and A0
Chip Select bits (Figure 5-2) should be set to ‘0’.
The last bit of the control byte defines the operation to
be performed. When set to a ‘1’, a read operation is
selected. When set to a ‘0’, a write operation is
selected. The next two bytes received define the
address of the first data byte (Figure 5-2). Because
only A12...A0 are used, the upper-three address bits
are “don’t care” bits. The upper-address bits are
transferred first, followed by the Less Significant bits.
Following the Start condition, the 24XX64F monitors
the SDA bus, checking the device-type identifier being
transmitted. Upon receiving a ‘1010’ code and appro-
priate device-select bits, the slave device outputs an
Acknowledge signal on the SDA line. Depending on the
state of the R/W bit, the 24XX64F will select a read or
write operation.
FIGURE 5-1:
CONTROL BYTE FORMAT
Read/Write Bit
Control Code
Chip Select
Bits
S 1 0 1 0 A2 A1 A0 R/W ACK
Start Bit
Slave Address
Acknowledge Bit
5.1 Contiguous Addressing Across
Multiple Devices
The Chip Select bits A2, A1 and A0 can be used to
expand the contiguous address space for up to 512K
bits by adding up to eight 24XX64F devices on the
same bus. In this case, software can use A0 of the con-
trol byte as address bit A13; A1 as address bit A14; and
A2 as address bit A15. It is not possible to sequentially
read across device boundaries.
The SOT-23 package does not support multiple device
addressing on the same bus.
FIGURE 5-2:
ADDRESS SEQUENCE BIT ASSIGNMENTS
Control Byte
Address High Byte
Address Low Byte
1
0
1
0
A
2
A
1
A
0
R/W
Control
Code
Chip
Select
bits
x
x
x
AA _A
12 11 10
A
9
A
8
A
7
•
•
•
•
•
•
A
0
x = “don’t care” bit
© 2009 Microchip Technology Inc.
DS22154A-page 7