24AA164 Datasheet, PDF (7/12 Pages) Microchip Technology – 16K 1.8V Cascadable I2CTM Serial EEPROM

24AA164
7.0 READ OPERATION
Read operations are initiated in the same way as write
operations with the exception that the R/W bit of the slave
address is set to one. There are three basic types of read
operations: current address read, random read, and
sequential read.
7.1 Current Address Read
The 24AA164 contains an address counter that maintains
the address of the last word accessed, internally incre-
mented by one. Therefore, if the previous access (either a
read or write operation) was to address n, the next current
address read operation would access data from address n
+ 1. Upon receipt of the slave address with R/W bit set to
one, the 24AA164 issues an acknowledge and transmits
the 8-bit data word. The master will not acknowledge the
transfer but does generate a stop condition and the
24AA164 discontinues transmission (Figure 7-1).
7.2 Random Read
Random read operations allow the master to access any
memory location in a random manner. To perform this
type of read operation, first the word address must be set.
This is done by sending the word address to the 24AA164
as part of a write operation. After the word address is sent,
the master generates a start condition following the
acknowledge. This terminates the write operation, but not
before the internal address pointer is set. Then the master
issues the control byte again but with the R/W bit set to a
one. The 24AA164 will then issue an acknowledge and
transmits the 8-bit data word. The master will not acknowl-
edge the transfer but does generate a stop condition and
the 24AA164 discontinues transmission (Figure 7-2).
7.3 Sequential Read
Sequential reads are initiated in the same way as a ran-
dom read except that after the 24AA164 transmits the
first data byte, the master issues an acknowledge as
opposed to a stop condition in a random read. This
directs the 24AA164 to transmit the next sequentially
addressed 8-bit word (Figure 7-3).
To provide sequential reads the 24AA164 contains an
internal address pointer which is incremented by one at
the completion of each operation. This address pointer
allows an entire device memory contents to be serially
read during one operation.
7.4 Noise Protection
The 24AA164 employs a VCC threshold detector circuit
which disables the internal erase/write logic if the VCC
is below 1.5 volts at nominal conditions.
The SCL and SDA inputs have Schmitt trigger and filter
circuits which suppress noise spikes to assure proper
device operation even on a noisy bus.
FIGURE 7-1:
CURRENT ADDRESS READ
BUS ACTIVITY
MASTER
S
T
A
BYTE
R CONTROL
T
S
T
DATA n
O
P
SDA LINE
BUS ACTIVITY
S 1 A2 A1 A0 B2 B1 B0
A
C
K
FIGURE 7-2: RANDOM READ
S
BUS ACTIVITY
MASTER
T
A
R
T
CONTROL
BYTE
SDA LINE
S ^{1 A2 A1A0B2B1B0}
A
C
BUS ACTIVITY
K
WORD
ADDRESS (n)
S
T
A
R
T
S
A
C
K
CONTROL
BYTE
FIGURE 7-3: SEQUENTIAL READ
BUS ACTIVITY
MASTER
CONTROL
BYTE
DATA n
DATA n + 1
DATA n + 2
P
N
O
A
C
K
S
T
DATA (n)
O
P
P
A
N
C
O
K
A
C
K
S
T
O
DATA n + X
P
SDA LINE
P
A
A
A
A
N
BUS ACTIVITY
C
C
C
C
O
K
K
K
K
A
C
K
DS21100F-page 7
© 1999 Microchip Technology Inc.