MCP454X_13 Datasheet, PDF (61/102 Pages) Microchip Technology – 7/8-Bit Single/Dual I2C Digital POT with Nonvolatile Memory

MCP454X/456X/464X/466X
Fixed
Address
Read bit
Variable
Address
Read Data bits
STOP bit
S 0 1 0 1 A2 A1 A0 1 A 0 0 0 0 0 0 0 D8 A¹ D7 D6 D5 D4 D3 D2 D1 D0 A² P
Control Byte
Read bits
Note 1: Master Device is responsible for A / A signal. If a A signal occurs, the MCP45XX/46XX will
abort this transfer and release the bus.
2: The Master Device will Not Acknowledge, and the MCP45XX/46XX will release the bus so the
Master Device can generate a Stop or Repeated Start condition.
3: The MCP45xx/46xx retains the last “Device Memory Address” that it has received. This is the
MCP45XX/46XX does not “corrupt” the “Device Memory Address” after Repeated Start or
Stop conditions.
4: The Device Memory Address pointer defaults to 00h on POR and BOR conditions.
FIGURE 7-4:
I²C Read (Last Memory Address Accessed).
Fixed
Address
Variable
Address
Write bit
Device
Memory
Address
Command
Repeated Start bit
S0
1
0
1 A2 A1 A0 0
A
AD AD AD AD
3210
1
1
xX
A Sr
Control Byte
READ Command
STOP bit
Read bit
Read Data bits
0 1 0 1 A2 A1 A0 1 A 0 0 0 0 0 0 0 D8 A¹ D7 D6 D5 D4 D3 D2 D1 D0 A² P
Control Byte
Read bits
Note 1: Master Device is responsible for A / A signal. If a A signal occurs, the MCP45XX/46XX will
abort this transfer and release the bus.
2: The Master Device will Not Acknowledge, and the MCP45XX/46XX will release the bus so the
Master Device can generate a Stop or Repeated Start condition.
3: The MCP45XX/46XX retains the last “Device Memory Address” that it has received. This is
the MCP45XX/46XX does not “corrupt” the “Device Memory Address” after Repeated Start or
Stop conditions.
FIGURE 7-5:
I²C Random Read.
 2008-2013 Microchip Technology Inc.
DS22107B-page 61