DSPIC30F6010A_07 Datasheet, PDF (61/236 Pages) Microchip Technology – High-Performance, 16-Bit Digital Signal Controllers

TABLE 8-1: dsPIC30F6010A PORT REGISTER MAP
SFR _{Addr. Bit 15}
Name
Bit 14 Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5 Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
TRISA
PORTA
LATA
TRISB
PORTB
LATB
TRISC
02C0 TRISA15 TRISA14 —
—
— TRISA10 TRISA9 —
—
—
—
—
—
—
—
—
02C2 RA15 RA14
—
—
—
RA10 RA9
—
—
—
—
—
—
—
—
—
02C4 LATA15 LATA14 —
—
— LATA10 LATA9 —
—
—
—
—
—
—
—
—
02C6 TRISB15 TRISB14 TRISB13 TRISB12 TRISB11 TRISB10 TRISB9 TRISB8 TRISB7 TRISB6 TRISB5 TRISB4 TRISB3 TRISB2 TRISB1 TRISB0
02C8 RB15 RB14 RB13 RB12 RB11 RB10 RB9 RB8 RB7 RB6 RB5 RB4 RB3 RB2 RB1 RB0
02CB LATB15 LATB14 LATB13 LATB12 LATB11 LATB10 LATB9 LATB8 LATB7 LATB6 LATB5 LATB4 LATB3 LATB2 LATB1 LATB0
02CC TRISC15 TRISC14 TRISC13 —
—
—
—
—
—
—
—
— TRISC3 — TRISC1 —
PORTC 02CE RC15 RC14 RC13
—
—
—
—
—
—
—
—
—
RC3
—
RC1
—
LATC
02D0 LATC15 LATC14 LATC13 —
—
—
—
—
—
—
—
— LATC3 — LATC1 —
TRISD
PORTD
LATD
TRISE
02D2 TRISD15 TRISD14 TRISD13 TRISD12 TRISD11 TRISD10 TRISD9 TRISD8 TRISD7 TRISD6 TRISD5 TRISD4 TRISD3 TRISD2 TRISD1 TRISD0
02D4 RD15 RD14 RD13 RD12 RD11 RD10 RD9 RD8 RD7 RD6 RD5 RD4 RD3 RD2 RD1 RD0
02D6 LATD15 LATD14 LATD13 LATD12 LATD11 LATD10 LATD9 LATD8 LATD7 LATD6 LATD5 LATD4 LATD3 LATD2 LATD1 LATD0
02D8 —
—
—
—
—
— TRISE9 TRISE8 TRISE7 TRISE6 TRISE5 TRISE4 TRISE3 TRISE2 TRISE1 TRISE0
PORTE 02DA —
—
—
—
—
—
RE9 RE8 RE7 RE6 RE5 RE4 RE3 RE2 RE1 RE0
LATE
02DC —
—
—
—
—
— LATE9 LATE8 LATE7 LATE6 LATE5 LATE4 LATE3 LATE2 LATE1 LATE0
TRISF
02EE —
—
—
—
—
—
— TRISF8 TRISF7 TRISF6 TRISF5 TRISF4 TRISF3 TRISF2 TRISF1 TRISF0
PORTF 02E0 —
—
—
—
—
—
—
RF8 RF7 RF6 RF5 RF4 RF3 RF2 RF1 RF0
LATF
TRISG
PORTG
LATG
Legend:
Note:
02E2 —
—
—
—
—
—
— LATF8 LATF7 LATF6 LATF5
02E4 —
—
—
—
—
— TRISG9 TRISG8 TRISG7 TRISG6 —
02E6 —
—
—
—
—
—
RG9 RG8 RG7 RG6
—
02E8 —
—
—
—
—
— LATG9 LATG8 LATG7 LATG6 —
u = uninitialized bit
Refer to “dsPIC30F Family Reference Manual” (DS70046) for descriptions of register bit fields.
LATF4 LATF3 LATF2 LATF1 LATF0
— TRISG3 TRISG2 TRISG1 TRISG0
—
RG3 RG2 RG1 RG0
— LATG3 LATG2 LATG1 LATG0
Reset State
1100 0110 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
1111 1111 1111 1111
0000 0000 0000 0000
0000 0000 0000 0000
1110 0000 0000 1010
0000 0000 0000 0000
0000 0000 0000 0000
1111 1111 1111 1111
0000 0000 0000 0000
0000 0000 0000 0000
0000 0011 1111 1111
0000 0000 0000 0000
0000 0000 0000 0000
0000 0001 1111 1111
0000 0000 0000 0000
0000 0000 0000 0000
0000 0011 1100 1111
0000 0000 0000 0000
0000 0000 0000 0000