DSPIC30F3010_07 Datasheet, PDF (60/220 Pages) Microchip Technology – High-Performance, 16-Bit Digital Signal Controllers

dsPIC30F3010/3011
FIGURE 8-2:
BLOCK DIAGRAM OF A SHARED PORT STRUCTURE
Peripheral Module
Peripheral Input Data
Peripheral Module Enable
Peripheral Output Enable
Peripheral Output Data
Output Multiplexers
I/O Cell
1 _{Output Enable}
0
PIO Module
1
Output Data
0
Read TRIS
Data Bus
WR TRIS
D
Q
CK
TRIS Latch
I/O Pad
WR LAT +
WR Port
D
Q
CK
Data Latch
Read LAT
Read Port
Input Data
8.2 Configuring Analog Port Pins
The use of the ADPCFG and TRIS registers control the
operation of the A/D port pins. The port pins that are
desired as analog inputs must have their correspond-
ing TRIS bit set (input). If the TRIS bit is cleared
(output), the digital output level (VOH or VOL) will be
converted.
When reading the PORT register, all pins configured as
analog input channel will read as cleared (a low level).
Pins configured as digital inputs will not convert an
analog input. Analog levels on any pin that is defined as
a digital input (including the ANx pins), may cause the
input buffer to consume current that exceeds the
device specifications.
8.2.1 I/O PORT WRITE/READ TIMING
One instruction cycle is required between a port
direction change or port write operation and a read
operation of the same port. Typically this instruction
would be a NOP.
EXAMPLE 8-1:
PORT WRITE/READ
EXAMPLE
MOV
MOV
NOP
btss
0xFF00, W0
W0, TRISBB
PORTB, #13
; Configure PORTB<15:8>
; as inputs
; and PORTB<7:0> as outputs
; Delay 1 cycle
; Next Instruction
DS70141D-page 58
Confidential
© 2007 Microchip Technology Inc.