TC1270_07 Datasheet, PDF (6/14 Pages) Microchip Technology – 4-Pin Reset Monitors

TC1270/TC1271
4.0 APPLICATIONS INFORMATION
4.1 V_CC Transient Rejection
The TC1270/TC1271 provides accurate V_CC
monitoring and Reset timing during power-up,
power-down, and brownout/sag conditions, and rejects
negative-going transients (glitches) on the power
supply line. Figure 4-3 shows the maximum transient
duration vs. maximum negative excursion (overdrive)
for glitch rejection. Any combination of duration and
overdrive that lays under the curve will not generate a
Reset signal. Combinations above the curve are
detected as a brown-out or power-down. Transient
immunity can be improved by adding a capacitor in
close proximity to the V_CC pin of the TC1270/TC1271.
V_CC
V_TH
Overdrive
Duration
400
T_A = +25°C
320
240
160
TC127LMJ
80
TC127xR/S/T
0
1
10
100
1000
RESET COMPARATOR OVERDRIVE,
V_TH - V_CC (mV)
FIGURE 4-1:
Maximum Transient
Duration vs. Overdrive for Glitch Rejection at
+25°C.
4.2 Reset Signal Integrity During
Power-Down
The TC1270 RESET output is valid to V_CC = 1.0V.
Below this voltage the output becomes an “open circuit”
and does not sink current. This means CMOS logic
inputs to the microprocessor will be floating at an
undetermined voltage. Most digital systems are
completely shut down well above this voltage.
However, in situations where RESET must be
maintained valid to V_CC = 0V, a pull-down resistor must
be connected from RESET to ground to discharge stray
capacitances and hold the output low (Figure 4-2). This
resistor value, though not critical, should be chosen
such that it does not appreciably load RESET under
normal operation (100 kΩ will be suitable for most
applications). Similarly, a pull-up resistor to V_CC is
required for the TC1271 to ensure a valid high RESET
for V_CC below 1.1V.
V_CC
V_CC
TC1270
RESET
GND
R1
100k
FIGURE 4-2:
V_CC = 0V.
Ensuring RESET Valid to
4.3 Processors With Bidirectional
I/O Pins
Some microprocessor’s (such as Motorola 68HC11)
have bidirectional Reset pins. Depending on the
current drive capability of the processor pin, an indeter-
minate logic level may result if there is a logic conflict.
This can be avoided by adding a 4.7 kΩ resistor in
series with the output of the TC1270/TC1271
(Figure 4-3). If there are other components in the sys-
tem which require a Reset signal, they should be buff-
ered so as not to load the Reset line. If the other
components are required to follow the Reset I/O of the
microprocessor, the buffer should be connected as
shown with the solid line.
Buffer
Buffered RESET
To Other System
Components
V_CC
V_CC
V_CC
TC1270
4.7k
μP
RESET
RESET
GND
GND
FIGURE 4-3:
Reset I/O.
Interfacing to Bidirectional
DS21381D-page 6
© 2007 Microchip Technology Inc.