TC1188 Datasheet, PDF (6/16 Pages) Microchip Technology – MAX8863/64 Pin Compatible, Low Dropout, 120 mA Linear Regulators

TC1188/TC1189
3.0 PIN DESCRIPTIONS
The descriptions of the pins are listed in Table 3-1.
TABLE 3-1: PIN FUNCTION TABLE
Symbol
Description
SHDN
GND
V_IN
V_OUT
GND
Active Low Shutdown Input. When the SHDN input is low (< 0.2V), the quiscent current for the
TC1188/TC1189 is reduced to 0.1 nA. When the input voltage to the SHDN pin is high (> 2.0V) the
output of the TC1188/TC1189 is enabled. For the TC1189 only, the output capacitor is discharged by
an internal switch when the SHDN is low.
Ground. Connect to ground.
Unregulated Input Voltage. The input voltage can range from 2.7V to 6.0V.
Regulator Output. Sources up to 120 mA. Bypass with a 1 µF, <1 Ω typical ESR capacitor to GND.
Connect to GND.
3.1 Detailed Description
The TC1188/TC1189 devices are fixed output, low
dropout linear regulators. Utilizing CMOS construction,
the internal quiescent current consumed by the regula-
tor is minimized when compared to older bipolar low
dropout regulators.
The LDO output voltage is sensed at the non-inverting
pin of the internal error amplifier. The internal voltage
reference is sensed at the inverting pin of the internal
error amplifier. The error amplifier adjusts the gate
source voltage of the internal P-channel pass device
until the divided down output voltage matches the inter-
nal reference voltage. When it does, the LDO output
voltage is in regulation.
The SHDN, when pulled low, is used to turn off the P-
Channel MOSFET and lower the internal quiescent
current to less than 1 µA maximum. For normal opera-
tion, the SHDN pin is pulled to a high level. (> 2.0V).
The TC1189 incorporates an internal N-Channel MOS-
FET, which is used to discharge the output capacitor
when shutdown. The TC1188 does not have the inter-
nal N-Channel MOSFET, therefore, when the device is
shutdown, the output voltage will decrease at a rate
which is dependant on the load current.
3.2 Turn-On Response
The turn-on response is defined as two separate
response categories: Wake-Up Time (t_WK) and Settling
Time (t_S).
The TC1188/TC1189 have fast wake-up times (10 µsec
typical) when released from shutdown. See Figure 3-1
for the wake-up time, designated as t_WK. The wake-up
time is defined as the time it takes for the output to rise
to 2% of the V_OUT value after being released from shut-
down.
The total turn on response is defined as the Settling
Time (t_S) (Figure 3-1). Settling Time (inclusive with t_WK)
is defined as the condition when the output is within 2%
of its fully enabled value (140 µsec typical) when
released from shutdown. The settling time of the output
voltage is dependent on load conditions and output
capacitance on V_OUT (RC response).
SHDN
V_IL
V_OUT
V_IH
t_S
98%
2%
t_WK
FIGURE 3-1:
Wake-Up Response Time.
3.3 Internal P-Channel Pass
Transistor
The Internal P-Channel MOSFET is operated in the lin-
ear region to regulate the LDO output voltage. The
RDSon of the P-Channel MOSFET is approximately
1.1 Ω, making the LDO able to regulate with little input
to output voltage differential, "Low Dropout". Another
benefit of using CMOS construction is that the P-Chan-
nel MOSFET is a voltage controlled device, so it
doesn't consume a fraction of the bias current required
of bipolar PNP LDOs.
DS21364B-page 6
 2002 Microchip Technology Inc.