93AA76A_12 Datasheet, PDF (6/36 Pages) Microchip Technology – 8K Microwire Compatible Serial EEPROM

93AA76A/B/C, 93LC76A/B/C, 93C76A/B/C
2.4 Erase
The ERASE instruction forces all data bits of the
specified address to the logical ‘1’ state. The rising
edge of CLK before the last address bit initiates the
write cycle.
FIGURE 2-1:
CS
ERASE TIMING
CLK
The DO pin indicates the Ready/Busy status of the
device if CS is brought high after a minimum of 250 ns
low (TCSL). DO at logical ‘0’ indicates that programming
is still in progress. DO at logical ‘1’ indicates that the
register at the specified address has been erased and
the device is ready for another instruction.
Note:
After the Erase cycle is complete, issuing
a Start bit and then taking CS low will clear
the Ready/Busy status from DO.
TCSL
Check Status
DI
1
1
1 AN AN-1 AN-2 ••• A0
High-Z
DO
TSV
Busy
TWC
TCZ
Ready
High-Z
2.5 Erase All (ERAL)
The Erase All (ERAL) instruction will erase the entire
memory array to the logical ‘1’ state. The ERAL cycle
is identical to the erase cycle, except for the different
opcode. The ERAL cycle is completely self-timed. The
rising edge of CLK before the last data bit initiates the
write cycle. Clocking of the CLK pin is not necessary
after the device has entered the ERAL cycle.
FIGURE 2-2:
ERAL TIMING
CS
The DO pin indicates the Ready/Busy status of the
device, if CS is brought high after a minimum of 250 ns
low (TCSL).
Note:
After the ERAL command is complete,
issuing a Start bit and then taking CS low
will clear the Ready/Busy status from DO.
VCC must be 4.5V for proper operation of ERAL.
TCSL
Check Status
CLK
DI
1
00
10
x •••
x
High-Z
DO
TSV
Busy
TEC
TCZ
Ready
High-Z
DS21796M-page 6
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