24AA256 Datasheet, PDF (6/12 Pages) Microchip Technology – 256K I 2 C CMOS Serial EEPROM

24AA256/24LC256
5.0 DEVICE ADDRESSING
A control byte is the first byte received following the
start condition from the master device (Figure 5-1). The
control byte consists of a 4-bit control code; for the
24xx256 this is set as 1010 binary for read and write
operations. The next three bits of the control byte are
the chip select bits (A2, A1, A0). The chip select bits
allow the use of up to eight 24xx256 devices on the
same bus and are used to select which device is
accessed. The chip select bits in the control byte must
correspond to the logic levels on the corresponding A2,
A1, and A0 pins for the device to respond. These bits
are in effect the three most significant bits of the word
address.
The last bit of the control byte defines the operation to
be performed. When set to a one a read operation is
selected, and when set to a zero a write operation is
selected. The next two bytes received define the
address of the first data byte (Figure 5-2). Because
only A14…A0 are used, the upper address bit is a don’t
care bit. The upper address bits are transferred first, fol-
lowed by the less significant bits.
Following the start condition, the 24xx256 monitors the
SDA bus checking the control byte being transmitted.
Upon receiving a 1010 code and appropriate device
select bits, the slave device outputs an acknowledge
signal on the SDA line. Depending on the state of
the R/W bit, the 24xx256 will select a read or write
operation.
FIGURE 5-1: CONTROL BYTE FORMAT
Read/Write Bit
Control Code
Chip Select
Bits
S 1 0 1 0 A2 A1 A0 R/W ACK
Start Bit
Slave Address
Acknowledge Bit
5.1 Contiguous Addressing Across
Multiple Devices
The chip select bits A2, A1, A0 can be used to expand
the contiguous address space for up to 2 Mbit
by adding up to eight 24xx256's on the same bus. In
this case, software can use A0 of the control byte as
address bit A15; A1, as address bit A16; and A2, as
address bit A17. It is not possible to read or write
across device boundaries.
FIGURE 5-2: ADDRESS SEQUENCE BIT ASSIGNMENTS
CONTROL BYTE
ADDRESS HIGH BYTE
ADDRESS LOW BYTE
1
0
1
0
A
2
A
1
A
0
R/W
CONTROL
CODE
CHIP
SELECT
BITS
X
A A AA A
14 13 12 11 10
A
9
A
8
X = Don’t Care Bit
A
7
•
•
•
•
•
•
A
0
DS21203C-page 6
© 1998 Microchip Technology Inc.