PIC16C433 Datasheet, PDF (58/126 Pages) Microchip Technology – 8-Bit CMOS Microcontroller with LIN Transceiver

PIC16C433
9.4 Power-on Reset (POR), Power-up
Timer (PWRT) and Oscillator Start-up
Timer (OST)
9.4.1 POWER-ON RESET (POR)
The on-chip POR circuit holds the chip in RESET until
VDD has reached a high enough level for proper oper-
ation. To take advantage of the POR, just tie the MCLR
pin through a resistor to VDD. This will eliminate exter-
nal RC components usually needed to create a Power-
on Reset. A maximum rise time for VDD is specified.
See Electrical Specifications for details.
When the device starts normal operation (exits the
RESET condition), device operating parameters (volt-
age, frequency, temperature, ...) must be met to ensure
operation. If these conditions are not met, the device
must be held in RESET until the operating conditions
are met.
For additional information, refer to Application Note
AN607, "Power-up Trouble Shooting."
9.4.2 POWER-UP TIMER (PWRT)
The Power-up Timer provides a fixed 72 ms nominal
timeout on power-up only, from the POR. The Power-
up Timer operates on an internal RC oscillator. The
chip is kept in RESET as long as the PWRT is active.
The PWRT’s time delay allows VDD to rise to an accept-
able level. A configuration bit is provided to enable/dis-
able the PWRT.
The power-up time delay will vary from chip to chip due
to VDD, temperature and process variation.
9.4.3 OSCILLATOR START-UP TIMER (OST)
The Oscillator Start-up Timer (OST) provides 1024
oscillator cycle (from OSC1 input) delay after the
PWRT delay is over. This ensures that the crystal oscil-
lator, or resonator has started and stabilized.
The OST timeout is invoked only for XT, LP and HS
modes and only on Power-on Reset or wake-up from
SLEEP.
9.4.4 TIMEOUT SEQUENCE
On power-up, the timeout Sequence is as follows: first,
PWRT timeout is invoked after the POR time delay has
expired; then, OST is activated. The total timeout will
vary, based on oscillator configuration and the status of
the PWRT. For example, in RC mode with the PWRT
disabled, there will be no timeout at all. Figure 9-7,
Figure 9-8, and Figure 9-9 depict timeout sequences
on power-up.
Since the timeouts occur from the POR pulse, if MCLR
is kept low long enough, the timeouts will expire. Then
bringing MCLR high will begin execution immediately
(Figure 9-9). This is useful for testing purposes, or to
synchronize more than one PIC16C433 device operat-
ing in parallel.
9.4.5 POWER CONTROL/STATUS REGISTER
(PCON)
The Power Control/Status Register, PCON (address
8Eh), has one bit.
Bit1 is POR (Power-on Reset). It is cleared on a Power-
on Reset and is unaffected otherwise. The user sets
this bit following a Power-on Reset. On subsequent
RESETS, if POR is ‘0’, it will indicate that a Power-on
Reset must have occurred.
TABLE 9-4: TIMEOUT IN VARIOUS SITUATIONS
Oscillator Configuration
XT, HS, LP
INTRC, EXTRC
Power-up
PWRTE = 0
72 ms + 1024TOSC
72 ms
PWRTE = 1
1024TOSC
—
Wake-up from SLEEP
1024TOSC
—
TABLE 9-5: STATUS/PCON BITS AND THEIR SIGNIFICANCE
POR
TO
PD
0
1
1
Power-on Reset
0
0
x
Illegal, TO is set on POR
0
x
0
Illegal, PD is set on POR
1
0
u
WDT Reset
1
0
0
WDT Wake-up
1
u
u
MCLR Reset during normal operation
1
1
0
MCLR Reset during SLEEP or interrupt Wake-up from SLEEP
Legend: u = unchanged, x = unknown
DS41139B-page 56
Preliminary
 2002 Microchip Technology Inc.