USB3318C-CP-TR Datasheet, PDF (54/73 Pages) Microchip Technology – Hi-Speed USB Transceiver with 1.8V-3.3V ULPI Interface - 13MHz Reference Clock

7.1.1.5
Hi-Speed USB Transceiver with 1.8V-3.3V ULPI Interface - 13MHz Reference Clock
Datasheet
Function Control
Address = 04-06h (read), 04h (write), 05h (set), 06h (clear)
FIELD NAME
XcvrSelect[1:0]
TermSelect
OpMode
Reset
SuspendM
Reserved
BIT ACCESS DEFAULT DESCRIPTION
1:0 rd/w/s/c
01b
Selects the required transceiver speed.
00b: Enables HS transceiver
01b: Enables FS transceiver
10b: Enables LS transceiver
11b: Enables FS transceiver for LS packets (FS
preamble automatically pre-pended)
2 rd/w/s/c
0b
Controls the DP and DM termination depending on
XcvrSelect, OpMode, DpPulldown, and DmPulldown.
The DP and DM termination is detailed in Table 5.1.
4:3 rd/w/s/c
00b
Selects the required bit encoding style during
transmit.
00b: Normal Operation
01b: Non-Driving
10b: Disable bit-stuff and NRZI encoding
11b: Reserved
5 rd/w/s/c
6 rd/w/s/c
7
rd
0b
Active high transceiver reset. This reset does not
reset the ULPI interface or register set. Automatically
clears after reset is complete.
1b
Active low PHY suspend. When cleared the PHY will
enter Low Power Mode as detailed in 6.2.6.
Automatically set when exiting Low Power Mode.
0b
Read only, 0.
7.1.1.6
Interface Control
Address = 07-09h (read), 07h (write), 08h (set), 09h (clear)
FIELD NAME
6-pin FsLsSerialMode
3-pin FsLsSerialMode
CarkitMode
ClockSuspendM
AutoResume
BIT ACCESS DEFAULT DESCRIPTION
0 rd/w/s/c
1 rd/w/s/c
2 rd/w/s/c
3 rd/w/s/c
4 rd/w/s/c
0b
When asserted the ULPI interface is redefined to the
6-pin Serial Mode. The PHY will automatically clear
this bit when exiting serial mode.
0b
When asserted the ULPI interface is redefined to the
3-pin Serial Mode. The PHY will automatically clear
this bit when exiting serial mode.
0b
When asserted the ULPI interface is redefined to the
Carkit interface. The PHY will automatically clear this
bit when exiting carkit mode.
0b
Enables Link to turn on 60MHz CLKOUT in serial or
carkit mode.
0b: Disable clock in serial or carkit mode.
1b: Enable clock in serial or carkit mode.
0b
Only applicable in Host mode. Enables the PHY to
automatically transmit resume signaling. This
function is detailed in Section 6.2.4.4.
Revision 2.1 (06-02-10)
54
DATASHEET
SMSC USB3318 REV C