PIC16F1509-ESO Datasheet, PDF (53/418 Pages) Microchip Technology – 20-Pin Flash, 8-Bit Microcontrollers with XLP Technology

5.2.2.4 Peripheral Clock Sources
The clock sources described in this chapter and the
Timer’s are available to different peripherals. Table 5-1
lists the clocks and timers available for each peripheral.
TABLE 5-1: PERIPHERAL CLOCK
SOURCES
ADC X X
CLC X X X X X X X X
COMP
X
X
CWG X
X
EUSART X
X
MSSP X
X
NCO X
X
PWM X
X
PWRT
X
TMR0 X
TMR1 X
X
X
TMR2 X
WDT
X
PIC16(L)F1508/9
5.2.2.5
Internal Oscillator Frequency
Selection
The system clock speed can be selected via software
using the Internal Oscillator Frequency Select bits
IRCF<3:0> of the OSCCON register.
The postscaled output of the 16 MHz HFINTOSC and
31 kHz LFINTOSC connect to a multiplexer (see
Figure 5-1). The Internal Oscillator Frequency Select
bits IRCF<3:0> of the OSCCON register (Register 5-1)
select the frequency output of the internal oscillators.
Note:
Following any Reset, the IRCF<3:0> bits
of the OSCCON register are set to ‘0111’
and the frequency selection is set to
500 kHz. The user can modify the IRCF
bits to select a different frequency.
The IRCF<3:0> bits of the OSCCON register allow
duplicate selections for some frequencies. These dupli-
cate choices can offer system design trade-offs. Lower
power consumption can be obtained when changing
oscillator sources for a given frequency. Faster transi-
tion times can be obtained between frequency changes
that use the same oscillator source.
5.2.2.6
Internal Oscillator Clock Switch
Timing
When switching between the HFINTOSC and the
LFINTOSC, the new oscillator may already be shut
down to save power (see Figure 5-7). If this is the case,
there is a delay after the IRCF<3:0> bits of the
OSCCON register are modified before the frequency
selection takes place. The OSCSTAT register will
reflect the current active status of the HFINTOSC and
LFINTOSC oscillators. The sequence of a frequency
selection is as follows:
1. IRCF<3:0> bits of the OSCCON register are
modified.
2. If the new clock is shut down, a clock start-up
delay is started.
3. Clock switch circuitry waits for a falling edge of
the current clock.
4. The current clock is held low and the clock
switch circuitry waits for a rising edge in the new
clock.
5. The new clock is now active.
6. The OSCSTAT register is updated as required.
7. Clock switch is complete.
See Figure 5-7 for more details.
If the internal oscillator speed is switched between two
clocks of the same source, there is no start-up delay
before the new frequency is selected. Clock switching
time delays are shown in Table 5-3.
Start-up delay specifications are located in Table 29-8,
“Oscillator Parameters”.
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DS40001609C-page 53