TC520A_13 Datasheet, PDF (5/16 Pages) Microchip Technology – Serial Interface Adapter for TC500 A/D Converter Family

TC520A
TABLE 2-1: PIN FUNCTION TABLE (CONTINUED)
Pin Number
14-Pin PDIP
12
13
14
Pin Number
16-Pin SOIC
14
15
16
Symbol
Description
LOAD
DV
CE
Input, active low; level and edge triggered. The LOAD VALUE is clocked into the 8-bit
shift register on board the TC520A while LOAD is held low. The LOAD VALUE is then
transferred into the TC520A internal timebase counter (and becomes effective) when
LOAD is returned high. If so desired, LOAD can be momentarily pulsed low, eliminating
the need to clock a LOAD VALUE into D_IN. In this case, the current state of D_IN is
clocked into the TC520A timebase counter selecting either a count of 65536
(D_IN = High), or count of 32768, (D_IN = Low).
Output, active low. DV is brought low any time the TC520A is in the AZ phase of con-
version. This occurs when, either the TC520A initiates a normal AZ phase by setting A,
B, equal to 01, or when CE is pulled high, which overrides the normal A, B sequencing
and forces an AZ state. DV is returned high when the TC520A exits AZ.
Input, active low, level triggered. Conversion will be continuously performed as long as
CE remains low. Pulling CE high causes the conversion process to be halted and
forces the TC520A into the AZ mode for as long as CE remains high. CE should be
taken high whenever it is necessary to momentarily suspend conversion (for example:
to change the address lines of an input multiplexer). CE should be pulled high only
when the TC520A enters an AZ phase (i.e. when DV is low). This is necessary to avoid
excessively long integrator discharge times, which could result in erroneous conver-
sion. This pin should be grounded if unused. It should be left floating if a 0.01F
RESET capacitor is connected to it (see Section 4.0, Typical Applications).
 2001-2012 Microchip Technology Inc.
DS21431C-page 5