TC14433 Datasheet, PDF (5/20 Pages) TelCom Semiconductor, Inc – 3-1/2 DIGIT A/D CONVERTERS

TC14433/A
2.0 PIN DESCRIPTIONS
The descriptions of the pins are listed in Table 2.0.
TABLE 2-1: PIN FUNCTION TABLE
Pin No.
(24-Pin PDIP)
(24-Pin CERDIP)
(24-Pin SOIC)
Pin No.
(28-Pin PLCC)
Symbol
Description
1
2
V_AG This is the analog ground. It has a high input impedance. The pin determines the
reference level for the unknown input voltage (V_X) and the reference voltage (V_REF).
2
3
V_REF Reference voltage - Full scale output is equal to the voltage applied to V_REF.
Therefore, full scale voltage of 1.999V requires 2V reference and 199.9mV full scale
requires a 200mV reference. V_REF functions as system reset also. When switched
to V_EE, the system is reset to the beginning of the conversion cycle.
3
4
V_X The unknown input voltage (V_X) is measured as a ratio of the reference voltage
(V_REF) in a rationetric A/D conversion.
4
5
R₁ This pin is for external components used for the integration function in the dual
slope conversion. Typical values are 0.1µF (mylar) capacitor for C₁.
5
6
R₁/C₁ R₁ = 470kΩ (resistor) for 2V full scale.
6
7
C₁ R₁ = 27kΩ (resistor) for 200mV full scale. Clock frequency of 66kHz gives 250msec
conversion time.
7
9
CO₁ These pins are used for connecting the offset correction capacitor.
The recommended value is 0.1µF.
8
10
CO₂ These pins are used for connecting the offset correction capacitor.
The recommended value is 0.1µF.
9
11
DU Display update input pin. When DU is connected to the EOC output, every
conversion is displayed. New data will be strobed into the output latches during the
conversion cycle if a positive edge is received on DU, prior to the ramp down cycle.
When this pin is driven from an external source, the voltage should be referenced
to V_SS.
10
12
CLK₁ Clock input pins. The TC14433 has its own oscillator system clock. Connecting a
single resistor between CLK₁ and CLK₀ sets the clock frequency.
11
13
CLK₀ A crystal or OC circuit may be inserted in lieu of a resistor for improved CLK₁ , the
clock input, can be driven from an external clock source, which need only have
standard CMOS output drive. This pin is referenced to V_EE for external clock inputs.
A 300kΩ resistor yields a clock frequency of about 66kHz. See Section 5.0 Typical
Characteristics. (Also see Figure 4-3 for alternate circuits.)
12
14
V_EE Negative power current. Connection pin for the most negative supply. Please note
the current for the output drive circuit is returned through V_SS. Typical supply
current is 0.8mA.
13
16
V_SS Negative power supply for output circuitry. This pin sets the low voltage level for the
output pins (BCD, Digit Selects, EOC, OR). When connected to analog ground, the
output voltage is from analog ground to V_DD. If connected to V_EE, the output swing
is from V_EE to V_DD. The recommended operating range for V_SS is between the
V_DD -3 volts and V_EE.
14
17
EOC End of conversion output generates a pulse at the end of each conversion cycle.
This generated pulse width is equal to one half the period of the system clock.
15
18
OR Overrange pin. Normally this pin is set high. When V_X exceeds V_REF the OR is low.
16
19
DS₄ Digit select pin. The digit select output goes high when the respective digit is
selected. The MSD (1/2 digit turns on immediately after an EOC pulse).
17
20
DS₃ The remaining digits turn on in sequence from MSD to LSD.
18
21
DS₂ To ensure that the BCD data has settled, an inter digit blanking time of two clock
periods is included.
19
23
DS₁ Clock frequency divided by 80 equals multiplex rate. For example, a system clock of
60kHz gives a multiplex rate of 0.8kHz.
20
24
Q₀ See Figure 4-4 for digit select timing diagram.
© 2002 Microchip Technology Inc.
DS21394B-page 5