TC1270 Datasheet, PDF (5/12 Pages) Microchip Technology – 4-Pin μP Reset Monitors

3.0 APPLICATIONS INFORMATION
3.1 V_CC Transient Rejection
The TC1270/TC1271 provides accurate V_CC monitor-
ing and reset timing during power-up, power-down, and
brownout/sag conditions, and rejects negative-going
transients (glitches) on the power supply line. Figure
3-1 shows the maximum transient duration vs.
maximum negative excursion (overdrive) for glitch
rejection. Any combination of duration and overdrive
that lays under the curve will not generate a reset
signal. Combinations above the curve are detected as
a brownout or power-down. Transient immunity can be
improved by adding a capacitor in close proximity to the
V_CC pin of the TC1270/TC1271.
FIGURE 3-1:
V_CC
MAXIMUM TRANSIENT
DURATION VS.
OVERDRIVE FOR GLITCH
REJECTION AT 25°C
V_TH
Overdrive
400
T_A
320
Duration
°C
240
160
TC127LMJ
80
TC127xR/S/T
0
1
10
100
1000
RESET COMPARATOR OVERDRIVE,
V_TH - V_CC (mV)
3.2 RESET Signal Integrity During
Power-Down
The TC1270 RESET output is valid to V_CC = 1.0V.
Below this voltage the output becomes an "open
circuit" and does not sink current. This means CMOS
logic inputs to the µP will be floating at an
undetermined voltage. Most digital systems are
completely shut down well above this voltage.
However, in situations where RESET must be
maintained valid to V_CC = 0V, a pull-down resistor must
© 2002 Microchip Technology Inc.
TC1270/TC1271
be connected from RESET to ground to discharge stray
capacitances and hold the output low (Figure 3-2). This
resistor value, though not critical, should be chosen
such that it does not appreciably load RESET under
normal operation (100kΩ will be suitable for most
applications). Similarly, a pull-up resistor to V_CC is
required for the TC1271 to ensure a valid high RESET
for V_CC below 1.1V.
FIGURE 3-2:
ENSURING RESET VALID
TO V_CC = 0V
V_CC
V_CC
TC1270
RESET
GND
R1
100k
3.3 Processors With Bidirectional
I/O Pins
Some µP's (such as Motorola 68HC11) have bi-
directional reset pins. Depending on the current drive
capability of the processor pin, an indeterminate logic
level may result if there is a logic conflict. This can be
avoided by adding a 4.7 kΩ resistor in series with the
output of the TC1270/TC1271 (Figure 3-3). If there are
other components in the system which require a reset
signal, they should be buffered so as not to load the
reset line. If the other components are required to
follow the reset I/O of the µP, the buffer should be
connected as shown with the solid line.
FIGURE 3-3:
V_CC
V_CC
TC1270
RESET
INTERFACING TO
BIDIRECTIONAL
RESET I/O
Buffer
Buffered RESET
To Other System
Components
V_CC
µP
4.7k
RESET
GND
GND
DS21381B-page 5