PIC18F8490 Datasheet, PDF (5/10 Pages) Microchip Technology – PIC18F6390/6490/8390/8490 Rev.B3 SILICON ERRATA

PIC18F6390/6490/8390/8490
11. Module: EUSART
When performing back-to-back transmission in 9-bit
mode (TX9D bit in the TXSTAx register is set), the
second byte may be corrupted if it is written into
TXREGx immediately after the TMRT bit is set.
Work around
Execute a software delay, at least one-half the
transmission’s bit time, after TMRT is set and prior
to writing subsequent bytes into TXREGx.
Date Codes that pertain to this issue:
All engineering and production devices.
12. Module: AUSART
The AUSART for PIC18F6390/6490/8390/8490
devices may not recognize a received Stop bit if
the combined error rate is too high.
Work around
1. Increase the baud rate of the device by
decrementing the SPBRGHx:SPBRGx register
pair value by one. Verify that the new baud rate
does not exceed the maximum combined error
rate of the application.
2. Configure the transmitter to send two Stop bits.
Date Codes that pertain to this issue:
All engineering and production devices.
13. Module: Timer1/Timer3
When Timer1 or Timer3 is configured for external
clock source and the CCPxCON register is
configured with 0x0B (Compare mode, trigger
special event), the timer is not reset on a Special
Event Trigger.
Work around
Modify firmware to reset the Timer1/Timer3
registers upon detection of the compare match
condition — TMRxL and TMRxH.
Date Codes that pertain to this issue:
All engineering and production devices.
14. Module: Timer1/Timer3
When Timer1 or Timer3 is in External Clock
Synchronized mode and the external clock period
is between 1 and 2 TCY, interrupts will occasionally
be skipped.
Work around
Avoid using an external clock with a period (1/
frequency) between 1 and 2 TCY.
Date Codes that pertain to this issue:
All engineering and production devices.
15. Module: Timer1/Timer3
When Timer1/Timer3 is operating in 16-bit mode
and the prescale setting is not 1:1, a write to the
TMR1H/TMR3H Buffer registers may lengthen the
duration of the period between the increments of
the timer for the period in which TMR1H/TMR3H
was written.
Work around
Two work arounds are available: 1) Stop Timer1/
Timer3 before writing the TMR1H/TMR3H
registers; 2) Write TMR1L/TMR3L immediately
after writing TMR1H/TMR3H.
Date Codes that pertain to this issue:
All engineering and production devices.
© 2005 Microchip Technology Inc.
DS80207B-page 5