27C256_04 Datasheet, PDF (5/10 Pages) Microchip Technology – 256K (32K x 8) CMOS EPROM

FIGURE 1-2: PROGRAMMING WAVEFORMS
27C256
VIH
Address
VIL
VIH
Data
VIL
13.0V(2)
VPP
5.0V
6.5V(2)
VCC
5.0V
VIH
CE
VIL
VIH
OE
VIL
Program
Address Stable
t AS
Data Stable
t DS
t DH
t VPS
t VCS
High Z
Verify
t AH
Data Out Valid
t DF
(1)
t PW
t OES
t OE
(1)
Notes:
(1) tDF and t OE are characteristics of the device but must be accommodated by the programmer
(2) VCC = 6.5 V ±0.25V, V PP = V H = 13.0V ±0.25V for express algorithm
TABLE 1-6: MODES
Operation Mode
Read
Program
Program Verify
Program Inhibit
Standby
Output Disable
Identity
X = Don’t Care
CE
OE
VPP
A9
VIL
VIL
VCC
X
VIL
VIH
VH
X
VIH
VIL
VH
X
VIH
VIH
VH
X
VIH
X
VCC
X
VIL
VIH
VCC
X
VIL
VIL
VCC
VH
O0 - O7
DOUT
DIN
DOUT
High Z
High Z
High Z
Identity Code
1.2 Read Mode
(See Timing Diagrams and AC Characteristics)
Read Mode is accessed when:
a) the CE pin is low to power up (enable) the chip
b) the OE pin is low to gate the data to the output
pins
For Read operations, if the addresses are stable, the
address access time (tACC) is equal to the delay from
CE to output (tCE). Data is transferred to the output
after a delay from the falling edge of OE (tOE).
 2004 Microchip Technology Inc.
DS11001N-page 5