24AA64_12 Datasheet, PDF (5/44 Pages) Microchip Technology – 64K I2C™ Serial EEPROM

24AA64/24LC64/24FC64
2.0 PIN DESCRIPTIONS
The descriptions of the pins are listed in Table 2-1.
TABLE 2-1: PIN FUNCTION TABLE
Name PDIP
SOIC
TSSOP
Rotated
TSSOP
DFN⁽¹⁾
TDFN⁽¹⁾
MSOP
SOT-23
CS
Description
A0 1
1
1
3
1
1
1
—
— Chip Address Input
A1 2
2
2
4
2
2
2
—
— Chip Address Input
A2 3
3
3
5
3
3
3
—
— Chip Address Input
VSS 4
4
4
6
4
4
4
2
2 Ground
SDA 5
5
5
7
5
5
5
3
5 Serial Address/Data I/O
SCL 6
6
6
8
6
6
6
1
4 Serial Clock
WP 7
7
7
1
7
7
7
5
3 Write-Protect Input
VCC 8
8
8
2
8
8
8
4
1 +1.7V to 5.5V Power Supply
Note 1: The exposed pad on the DFN/TDFN packages can be connected to VSS or left floating.
2.1 A0, A1, A2 Chip Address Inputs
The A0, A1 and A2 inputs are used by the 24XX64 for
multiple device operation. The levels on these inputs
are compared with the corresponding bits in the slave
address. The chip is selected if the compare is true.
Up to eight devices may be connected to the same bus
by using different Chip Select bit combinations. These
inputs must be connected to either VCC or VSS.
In most applications, the chip address inputs A0, A1
and A2 are hard-wired to logic ‘0’ or logic ‘1’. For
applications in which these pins are controlled by a
microcontroller or other programmable device, the chip
address pins must be driven to logic ‘0’ or logic ‘1’
before normal device operation can proceed. Address
pins are not available in the SOT-23 or Chip Scale
packages.
2.2 Serial Data (SDA)
SDA is a bidirectional pin used to transfer addresses
and data into and out of the device. Since it is an open-
drain terminal, the SDA bus requires a pull-up resistor
to VCC (typical 10 k for 100 kHz, 2 kfor 400 kHz).
For normal data transfer, SDA is allowed to change
only during SCL low. Changes during SCL high are
reserved for indicating the Start and Stop conditions.
2.3 Serial Clock (SCL)
The SCL input is used to synchronize the data transfer
from and to the device.
2.4 Write-Protect (WP)
This pin must be connected to either VSS or VCC. If tied
to VSS, write operations are enabled. If tied to VCC,
write operations are inhibited but read operations are
not affected.
3.0 FUNCTIONAL DESCRIPTION
The 24XX64 supports a bidirectional, 2-wire bus and
data transmission protocol. A device that sends data
onto the bus is defined as transmitter, while a device
receiving data is defined as a receiver. The bus has to
be controlled by a master device which generates the
Serial Clock (SCL), controls the bus access and
generates the Start and Stop conditions, while the
24XX64 works as slave. Both master and slave can
operate as transmitter or receiver, but the master
device determines which mode is activated.
 1997-2012 Microchip Technology Inc.
DS21189T-page 5