KSZ9031RNX Datasheet, PDF (49/78 Pages) Micrel Semiconductor – Gigabit Ethernet Transceiver with RGMII Support

KSZ9031RNX
TABLE 4-6: MMD REGISTER DESCRIPTIONS (CONTINUED)
Address Name
Description
Mode
Note 4-1
Default
MMD Address 2h, Register 12h – Wake-On-LAN – Magic Packet, MAC-DA-1
2.12.15:0
Magic Packet This register stores the middle two bytes of the
RW
MAC-DA-1 destination MAC address for the magic packet.
Bit [15:8] = Byte 4 (MAC Address [31:24])
Bit [7:0] = Byte 3 (MAC Address [23:16])
The lower two bytes and upper two bytes of the
destination MAC address are stored in the previous
and following registers, respectively.
MMD Address 2h, Register 13h – Wake-On-LAN – Magic Packet, MAC-DA-2
0000_0000_0000_00
00
2.13.15:0 MagicPacket This register stores the upper two bytes of the
RW
MAC-DA-2 destination MAC address for the magic packet.
Bit [15:8] = Byte 6 (MAC Address [47:40])
Bit [7:0] = Byte 5 (MAC Address [39:32])
The lower four bytes of the destination MAC
address are stored in the previous two registers.
0000_0000_0000_00
00
MMD Address 2h, Register 14h – Wake-On-LAN – Customized Packet, Type 0, Expected CRC 0
MMD Address 2h, Register 16h – Wake-On-LAN – Customized Packet, Type 1, Expected CRC 0
MMD Address 2h, Register 18h – Wake-On-LAN – Customized Packet, Type 2, Expected CRC 0
MMD Address 2h, Register 1Ah – Wake-On-LAN – Customized Packet, Type 3, Expected CRC 0
2.14.15:0 Custom
This register stores the upper two bytes for the
RW
2.16.15:0 Packet Type expected CRC.
2.18.15:0 X CRC 0
Bit [15:8] = Byte 2 (CRC [15:8])
2.1A.15:0
Bit [7:0] = Byte 1 (CRC [7:0])
The lower two bytes for the expected CRC are
stored in the following register.
0000_0000_0000_00
00
MMD Address 2h, Register 15h – Wake-On-LAN – Customized Packet, Type 0, Expected CRC 1
MMD Address 2h, Register 17h – Wake-On-LAN – Customized Packet, Type 1, Expected CRC 1
MMD Address 2h, Register 19h – Wake-On-LAN – Customized Packet, Type 2, Expected CRC 1
MMD Address 2h, Register 1Bh – Wake-On-LAN – Customized Packet, Type 3, Expected CRC 1
2.15.15:0 Custom
This register stores the lower two bytes for the
RW
2.17.15:0 Packet Type expected CRC.
2.19.15:0 X CRC 1
Bit [15:8] = Byte 4 (CRC [31:24])
2.1B.15:0
Bit [7:0] = Byte 3 (CRC [23:16])
The upper two bytes for the expected CRC are
stored in the previous register.
0000_0000_0000_00
00
MMD Address 2h, Register 1Ch – Wake-On-LAN – Customized Packet, Type 0, Mask 0
MMD Address 2h, Register 20h – Wake-On-LAN – Customized Packet, Type 1, Mask 0
MMD Address 2h, Register 24h – Wake-On-LAN – Customized Packet, Type 2, Mask 0
MMD Address 2h, Register 28h – Wake-On-LAN – Customized Packet, Type 3, Mask 0
2.1C.15:0
2.20.15:0
2.24.15:0
2.28.15:0
Custom
Packet Type
X Mask 0
This register selects the bytes in the first 16 bytes RW
of the packet (bytes 1 through 16) that will be used
for CRC calculation.
For each bit in this register,
1 = Byte is selected for CRC calculation
0 = Byte is not selected for CRC calculation
The register-bit to packet-byte mapping is as fol-
lows:
Bit [15]: Byte 16
……
Bit [2]: Byte 2
Bit [0]: Byte 1
0000_0000_0000_00
00
 2016 Microchip Technology Inc.
DS00002117C-page 49