MCP47DA1 Datasheet, PDF (48/76 Pages) Microchip Technology – 6-Bit Windowed Volatile DAC with Command Code

MCP47DA1
7.2 Output Slew Rate
Figure 7-3 shows an example of the slew rate of the
V_OUT pin. The slew rate can be affected by the
characteristics of the circuit connected to the V_OUT pin.
V_OUT(B)
V_OUT(A)
Wiper = A
Wiper = B
Time
Slew Rate = ^{| VOUT(B) - VOUT(A) |}
T
FIGURE 7-3:
V_OUT pin Slew Rate.
7.2.1 SMALL CAPACITIVE LOAD
With a small capacitive load, the output buffer’s current
is not affected by the capacitive load (C_L). But still, the
V_OUT pin’s voltage is not a step transition from one
output value (wiper code value) to the next output
value. The change of the V_OUT voltage is limited by the
output buffer’s characteristics, so the V_OUT pin voltage
will have a slope from the old voltage to the new
voltage. This slope is fixed for the output buffer, and is
referred to as the buffer slew rate (SR_BUF).
7.2.2 LARGE CAPACITIVE LOAD
With a larger capacitive load, the slew rate is deter-
mined by two factors:
• The output buffer’s short circuit current (I_SC)
• The V_OUT pin’s external load
I_OUT cannot exceed the output buffer’s short circuit
current (I_SC), which fixes the output buffer slew rate
(SR_BUF). The voltage on the capacitive load (C_L), V_CL,
changes at a rate proportional to I_OUT, which fixes a
capacitive load slew rate (SR_CL).
So the V_CL voltage slew rate is limited to the slower of
the output buffer’s internally set slew rate (SRBUF) and
the capacitive load slew rate (SR_CL).
7.3 Driving Resistive and Capacitive
Loads
The V_OUT pin can drive up to 100 pF of capacitive load
in parallel with a 5 k resistive load (to meet electrical
specifications). Figure 2-84 shows the V_OUT vs.
Resistive Load.
V_OUT drops slowly as the load resistance decreases
after about 3.5 k . It is recommended to use a load
with R_L greater than 5 k.
Driving large capacitive loads can cause stability
problems for voltage feedback op amps. As the load
capacitance increases, the feedback loop’s phase
margin decreases and the closed-loop bandwidth is
reduced. This produces gain peaking in the frequency
response with overshoot and ringing in the step
response. That is, since the V_OUT pin’s voltage does
not quickly follow the buffer’s input voltage (due to the
large capacitive load), the output buffer will overshoot
the desired target voltage. Once the driver detects this
overshoot, it compensates by forcing it to a voltage
below the target. This causes voltage ringing on the
V_OUT pin.
So, when driving large capacitive loads with the output
buffer, a small series resistor (R_ISO) at the output (see
Figure 7-4) improves the output buffer’s stability (feed-
back loop’s phase margin) by making the output load
resistive at higher frequencies. The bandwidth will be
generally lower than the bandwidth with no capacitive
load.
V_W Op
Amp
V_OUT
R_ISO
V_CL
R_L
C_L
FIGURE 7-4:
Circuit to Stabilize Output
Buffer for Large Capacitive Loads (C_L).
The R_ISO resistor value for your circuit needs to be
selected. The resulting frequency response peaking
and step response overshoot for this R_ISO resistor
value should be verified on the bench. Modify the
R_ISO’s resistance value until the output characteristics
meet your requirements.
A method to evaluate the system’s performance is to
inject a step voltage on the V_REF pin and observe the
V_OUT pin’s characteristics.
Note:
Additional insight into circuit design for
driving capacitive loads can be found in
AN884, “Driving Capacitive Loads With
Op Amps” (DS00884).
DS25118D-page 48
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