ENC28J60_06 Datasheet, PDF (48/96 Pages) Microchip Technology – Stand-Alone Ethernet Controller with SPI Interface

ENC28J60
TABLE 7-4: SUMMARY OF REGISTERS USED FOR PACKET RECEPTION
Register
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Reset
Values
on page
EIE
INTIE
PKTIE
DMAIE
LINKIE
TXIE
r
TXERIE RXERIE
13
EIR
—
PKTIF
DMAIF
LINKIF
TXIF
r
TXERIF RXERIF
13
ESTAT
INT
BUFER
r
LATECOL
—
RXBUSY TXABRT CLKRDY
13
ECON2
AUTOINC PKTDEC PWRSV
r
VRPS
—
—
—
13
ECON1
TXRST
RXRST
DMAST CSUMEN TXRTS
RXEN
BSEL1
BSEL0
13
ERXSTL
RX Start Low Byte (ERXST<7:0>)
13
ERXSTH
—
—
—
RX Start High Byte (ERXST<12:8>)
13
ERXNDL RX End Low Byte (ERXND<7:0>)
13
ERXNDH
—
—
—
RX End High Byte (ERXND<12:8>)
13
ERXRDPTL RX RD Pointer Low Byte (ERXRDPT<7:0>)
13
ERXRDPTH
—
—
—
RX RD Pointer High Byte (ERXRDPT<12:8>)
13
ERXFCON
UCEN
ANDOR CRCEN
PMEN
MPEN
HTEN
MCEN
BCEN
14
EPKTCNT Ethernet Packet Count
14
MACON1
—
—
—
r
TXPAUS RXPAUS PASSALL MARXEN
14
MACON3 PADCFG2 PADCFG1 PADCFG0 TXCRCEN PHDREN HFRMEN FRMLNEN FULDPX
14
MAMXFLL Maximum Frame Length Low Byte (MAMXFL<7:0>)
14
MAMXFLH Maximum Frame Length High Byte (MAMXFL<15:8>)
14
Legend: — = unimplemented, r = reserved bit. Shaded cells are not used.
DS39662B-page 46
Preliminary
© 2006 Microchip Technology Inc.