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EMC1704 Datasheet, PDF (44/68 Pages) Microchip Technology – High-Side Current-Sense and Multiple 1°C Temperature Monitor
High-Side Current-Sense and Multiple 1°C Temperature Monitor
Datasheet
5.10 External Diode Fault Register
Table 5.11 External Diode Fault Register
ADDR. R/W REGISTER B7
B6
B5
B4
B3
B2
B1
B0 DEFAULT
1Bh
R-C
External
-
-
-
- E3FLT E2FLT E1FLT -
00h
Diode Fault
The External Diode Fault Register indicates which of the external diodes caused the FAULT bit in the
Status Register to be set. This register is cleared when it is read.
Bit 3 - E3FLT - This bit is set if the External Diode 3 channel reported a diode fault.
Bit 2 - E2FLT - This bit is set if the External Diode 2 channel reported a diode fault.
Bit 1 - E1FLT - This bit is set if the External Diode 1 channel reported a diode fault.
5.11 Channel Mask Register
Table 5.12 Channel Mask Register
ADDR R/W REGISTER
B7
B6
B5
1Fh R/W Channel VSENSE_ VSRC_ PEAK_
Mask
MASK
MASK MASK
B4
B3
B2
B1
B0 DEFAULT
-
E3
E2
E1
INT
00h
MASK MASK MASK MASK
EMC1704
The Channel Mask Register controls individual channel masking. When a channel is masked, the
ALERT pin will not be asserted when the masked channel reads a diode fault or out-of-limit error. The
channel mask does not mask the THERM pin.
Bit 7 - VSENSE_MASK - Masks the ALERT pin from asserting when the VSENSE value meets or
exceeds the high limit or drops below the low limit. This bit will have no effect on the THERM pin
functionality.
 ‘0’ (default) - The VSENSE voltage channel will cause the ALERT pin to be asserted (if enabled).
 ‘1’ - The VSENSE voltage channel will not cause the ALERT pin to be asserted (if enabled).
Bit 6 - VSRC_MASK - Masks the ALERT pin from asserting when the VSOURCE value meets or
exceeds the high limit or drops below the low limit. This bit will have no effect on the THERM pin
functionality.
 ‘0’ (default) - The VSOURCE voltage channel will cause the ALERT pin to be asserted (if enabled).
 ‘1’ - The VSOURCE voltage channel will not cause the ALERT pin to be asserted (if enabled).
BIt 5 - PEAK_MASK - Masks the ALERT pin from asserting when the Peak Detector circuitry detects
a current spike. This bit will have no effect on the THERM pin functionality.
 ‘0’ (default) - The Peak Detector circuitry will cause the ALERT pin to be asserted (if enabled).
 ‘1’ - The Peak Detector circuitry will not cause the ALERT pin to be asserted (if enabled).
Bit 3 - E3MASK - Masks the ALERT pin from asserting when the External Diode 3 channel is out-of-
limit or reports a diode fault.
 ‘0’ (default) - The External Diode 3 channel will cause the ALERT pin to be asserted if it is out-of-
limit or reports a diode fault.
 ‘1’ - The External Diode 3 channel will not cause the ALERT pin to be asserted if it is out-of-limit
or reports a diode fault.
44
DATASHEET
DS20005239A