MCP3903 Datasheet, PDF (40/54 Pages) Microchip Technology – Six Channel Delta Sigma A/D Converter

MCP3903
7.3 Phase Register
TABLE 7-5: PHASE REGISTER
Name
Bits
Address
Cof
PHASE
24
0x07
R/W
The reference channel is the odd channel (Channel 1/
3/5). When PHASEn<7:0> is positive, Channel 0/2/4 is
lagging versus channel 1/3/5 otherwise it is leading.
The delay is calculated by the following formula:
Delay = PHASE Register Code / DMCLK.
The phase register is composed of three bytes:
PHASEC<7:0>, PHASEB<7:0>, PHASEA<7:0>. Each
byte is a 7 bit + sign MSB first, two's complement code
that represents the amount of delay between each pair
of ADCs. The PHASEC byte represents the delay
between Channel 4 and Channel 5 (pair C). The
PHASEB byte represents the delay between Channel 2
and Channel 3 (pair B). The PHASEA byte represents
the delay between Channel 0 and Channel 1 (pair A).
REGISTER 7-3:
PHASE REGISTER
R/W-0
PHASEC7
bit 23
R/W-0
PHASEC6
R/W-0
PHASEC5
R/W-0
R/W-0
PHASEC4 PHASEC3
R/W-0
PHASEC2
R/W-0
PHASEC1
R/W-0
PHASEC0
bit 16
R/W-0
PHASEB7
bit 15
R/W-0
PHASEB6
R/W-0
R/W-0
R/W-0
PHASEB5 PHASEB4 PHASEB3
R/W-0
PHASEB2
R/W-0
PHASEB1
R/W-0
PHASEB0
bit 8
R/W-0
PHASEA7
bit 7
R/W-0
PHASEA6
R/W-0
R/W-0
R/W-0
PHASEA5 PHASEA4 PHASEA3
R/W-0
PHASEA2
R/W-0
PHASEA1
R/W-0
PHASEA0
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
bit 23:16
bit 15:8
bit 7:0
PHASECn: CH4 relative to CH5 phase delay
PHASEBn: CH2 relative to CH3 phase delay
PHASEAn: CH0 relative to CH1 phase delay
DS25048B-page 40
© 2011 Microchip Technology Inc.