TC520A Datasheet, PDF (4/16 Pages) TelCom Semiconductor, Inc – SERIAL INTERFACE ADAPTER FOR TC500 A/D CONVERTER FAMILY

TC520A
2.0 PIN DESCRIPTIONS
The descriptions of the pins are listed in Table 2-1
TABLE 2-1: PIN FUNCTION TABLE
Pin Number
14-Pin PDIP
1
2
3
4
5
6
7
8
9
10
11
Pin Number
16-Pin SOIC
1
2
3
4
5
6
7
8
9
10
11
12
13
Symbol
Description
V_DD Input. +5V ±10% power supply input with respect to DGND.
DGND Input. Digital Ground.
CMPTR
Input, active high or low (depending on polarity of the voltage input to A/D converter).
This pin connects directly to the zero crossing comparator output (CMPTR) of the
TC5XX A/D converter. A high-to-low state change on this pin causes the TC520A to
terminate the de-integrate phase of conversion.
B
Output, active high. The A and B outputs of the TC520A connect directly to the A and B
inputs of the TC5XX A/D converter connected to the TC520A. The binary code on A, B
determines the conversion phase of the TC5XX A/D converter: (A, B) = 01 places the
TC5XX A/D converter into the Auto Zero phase; (A, B) =10 for Integrate phase (INT);
(A, B) =11 for De-integrate phase (DINI) and (A, B) = 00 for Integrator Zero phase (IZ).
Please see the TC500/TC500A/TC510/TC514 family data sheets for a complete
description of these phases of operation.
A
Output, active high. See pin 4 description above.
OSC_OUT Input. This pin connects to one side of an AT-cut crystal having a effective series resis-
tance of 100Ω (typ.) and a parallel capacitance of 20pF (typ.). If an external frequency
source is used to clock the TC520A, this pin must be left floating.
OSC_IN
Input. This pin connects to the other side of the crystal described in pin 6 above. The
TC520A may also be clocked from an external frequency source connected to this pin.
The external frequency source must be a pulse train having a duty cycle of 30% (mini-
mum); rise and fall times of 15nsec and a min/max amplitude of 0 to V_IH. If an external
frequency source is used, pin 6 must be left floating. A maximum operating frequency
of 4MHz (crystal) or 6MHz (external clock source) is permitted.
N/C No connection on 16 pin package version.
N/C No connection on 16 pin package version.
READ
Input, active low, level and negative edge triggered. A high-to-low transition on READ
loads serial port output shift register with the most recent converted data. Data is
loaded such that the first bit transmitted from the TC520A to the processor is the
OVERRANGE bit (OVR), followed by the POLARITY bit (POL) (high = input positive;
low = input negative). This is followed by a 16-bit data word (MSB first). OVR is avail-
able at the D_OUT as soon as READ is brought low. This bit may be used as the 17th
data bit, if so desired. The D_OUT pin of the serial port is enabled only when READ is
held low. Otherwise, D_OUT remains in a high impedance state. A serial port read access
cycle is terminated at any time by bringing READ high.
D_OUT Output, logic level. Serial port output pin. This pin is enabled only when READ is low
(see READ pin description).
D_CLK
Input, positive and negative edge triggered. Serial port clock. With READ low, serial
data is clocked into the TC520A at each low-to-high transition of D_CLK, and clocked out
of the TC520A on each high-to-low transition of D_CLK. A maximum serial port D_CLK
frequency of 3MHz is permitted.
D_IN Input, logic level. Serial port input pin. The TC5XX A/D converter integration time (T_INT)
and Auto Zero time (TAZ) values are determined by the LOAD VALUE byte clocked into
this pin. This initialization must take place at power up and can be rewritten (or modified
and rewritten) at any time. The LOAD VALUE is clocked into D_IN MSB first.
DS21431B-page 4
© 2002 Microchip Technology Inc.